Add a register class -> virtual registers map.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57844 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/MachineRegisterInfo.h b/include/llvm/CodeGen/MachineRegisterInfo.h
index b851fdf66da9496d27bb402c6330b276d9afbc1a..2f25a5e140bf40bc1e16efc6d01fc92b21ba1635 100644 (file)
--- a/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -32,6 +32,11 @@ class MachineRegisterInfo {
   /// Each element in this list contains the register class of the vreg and the
   /// start of the use/def list for the register.
   std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
+
+  /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
+  /// virtual registers. For each target register class, it keeps a list of
+  /// virtual registers belonging to the class.
+  std::vector<std::vector<unsigned> > RegClass2VRegMap;
   
   /// PhysRegUseDefLists - This is an array of the head of the use/def list for
   /// physical registers.
@@ -130,6 +135,7 @@ public:
   //===--------------------------------------------------------------------===//
   
   /// getRegClass - Return the register class of the specified virtual register.
+  ///
   const TargetRegisterClass *getRegClass(unsigned Reg) const {
     Reg -= TargetRegisterInfo::FirstVirtualRegister;
     assert(Reg < VRegInfo.size() && "Invalid vreg!");
@@ -137,10 +143,22 @@ public:
   }
 
   /// setRegClass - Set the register class of the specified virtual register.
+  ///
   void setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
+    unsigned VR = Reg;
     Reg -= TargetRegisterInfo::FirstVirtualRegister;
     assert(Reg < VRegInfo.size() && "Invalid vreg!");
+    const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
     VRegInfo[Reg].first = RC;
+
+    // Remove from old register class's vregs list. This may be slow but
+    // fortunately this operation is rarely needed.
+    std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
+    std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR);
+    VRegs.erase(I);
+
+    // Add to new register class's vregs list.
+    RegClass2VRegMap[RC->getID()].push_back(VR);
   }
   
   /// createVirtualRegister - Create and return a new virtual register in the
@@ -151,13 +169,13 @@ public:
     // Add a reg, but keep track of whether the vector reallocated or not.
     void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
     VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
-    
-    if (&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)
-      return getLastVirtReg();
 
-    // Otherwise, the vector reallocated, handle this now.
-    HandleVRegListReallocation();
-    return getLastVirtReg();
+    if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
+      // The vector reallocated, handle this now.
+      HandleVRegListReallocation();
+    unsigned VR = getLastVirtReg();
+    RegClass2VRegMap[RegClass->getID()].push_back(VR);
+    return VR;
   }
 
   /// getLastVirtReg - Return the highest currently assigned virtual register.
@@ -165,7 +183,12 @@ public:
   unsigned getLastVirtReg() const {
     return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
   }
-  
+
+  /// getRegClassVirtRegs - Return the list of virtual registers of the given
+  /// target register class.
+  std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
+    return RegClass2VRegMap[RC->getID()];
+  }
   
   //===--------------------------------------------------------------------===//
   // Physical Register Use Info

diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp
index c247a22d23e70a00059b0d274820a0c08570de73..5e20689e0f6b0218e6ee943f0ee4d4ada1f1ae1f 100644 (file)
--- a/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/lib/CodeGen/MachineRegisterInfo.cpp
@@ -16,6 +16,7 @@ using namespace llvm;
 
 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
   VRegInfo.reserve(256);
+  RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1.
   UsedPhysRegs.resize(TRI.getNumRegs());
   
   // Create the physreg use/def lists.