Give ATTR_VEX higher priority when generating the disassembler context table. Fixes...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138552 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt
index b1442315d1d474ca3be7f0dd99b12fe5dd6cfb84..4e1bedd3cbaf79a7bac8bf0b726c337a5e3f6ec9 100644 (file)
--- a/test/MC/Disassembler/X86/simple-tests.txt
+++ b/test/MC/Disassembler/X86/simple-tests.txt
@@ -84,3 +84,6 @@
 
 # CHECK: vcvtps2pd %xmm0, %ymm0
 0xc5 0xfc 0x5a 0xc0
+
+# CHECK: vandps (%rdx), %xmm1, %xmm7
+0xc5 0xf0 0x54 0x3a

diff --git a/utils/TableGen/X86DisassemblerTables.cpp b/utils/TableGen/X86DisassemblerTables.cpp
index 74310593d29df399ca399f82541e5b813cf0524f..3e48c0b6f32ee5297132af436ccb71ab2c34fee3 100644 (file)
--- a/utils/TableGen/X86DisassemblerTables.cpp
+++ b/utils/TableGen/X86DisassemblerTables.cpp
@@ -515,6 +515,8 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const {
       o << "IC_VEX_XD";
     else if ((index & ATTR_VEX) && (index & ATTR_XS))
       o << "IC_VEX_XS";
+    else if (index & ATTR_VEX)
+      o << "IC_VEX";
     else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
       o << "IC_64BIT_REXW_XS";
     else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
@@ -538,8 +540,6 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const {
       o << "IC_XD";
     else if (index & ATTR_OPSIZE)
       o << "IC_OPSIZE";
-    else if (index & ATTR_VEX)
-      o << "IC_VEX";
     else
       o << "IC";