if (!isIntN(16, Value) && Ctx)
Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
break;
+ case Mips::fixup_MIPS_PC19_S2:
+ // Forcing a signed division because Value can be negative.
+ Value = (int64_t)Value / 4;
+ // We now check if Value can be encoded as a 19-bit signed immediate.
+ if (!isIntN(19, Value) && Ctx)
+ Ctx->FatalError(Fixup.getLoc(), "out of range PC19 fixup");
+ break;
case Mips::fixup_Mips_26:
// So far we are only using this type for jumps.
// The displacement is then divided by 4 to give us an 28 bit
{ "fixup_Mips_GOT_LO16", 0, 16, 0 },
{ "fixup_Mips_CALL_HI16", 0, 16, 0 },
{ "fixup_Mips_CALL_LO16", 0, 16, 0 },
+ { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_Mips_GOT_LO16", 16, 16, 0 },
{ "fixup_Mips_CALL_HI16", 16, 16, 0 },
{ "fixup_Mips_CALL_LO16", 16, 16, 0 },
+ { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
case Mips::fixup_MICROMIPS_TLS_TPREL_LO16:
Type = ELF::R_MICROMIPS_TLS_TPREL_LO16;
break;
+ case Mips::fixup_MIPS_PC19_S2:
+ Type = ELF::R_MIPS_PC19_S2;
+ break;
case Mips::fixup_MIPS_PC21_S2:
Type = ELF::R_MIPS_PC21_S2;
break;
// resulting in - R_MIPS_CALL_LO16
fixup_Mips_CALL_LO16,
+ // resulting in - R_MIPS_PC19_S2
+ fixup_MIPS_PC19_S2,
+
// resulting in - R_MIPS_PC21_S2
fixup_MIPS_PC21_S2,
MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
- assert(MI.getOperand(OpNo).isImm());
- // The immediate is encoded as 'immediate << 2'.
- unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
- assert((Res & 3) == 0);
- return Res >> 2;
+ const MCOperand &MO = MI.getOperand(OpNo);
+ if (MO.isImm()) {
+ // The immediate is encoded as 'immediate << 2'.
+ unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
+ assert((Res & 3) == 0);
+ return Res >> 2;
+ }
+
+ assert(MO.isExpr() &&
+ "getSimm19Lsl2Encoding expects only expressions or an immediate");
+
+ const MCExpr *Expr = MO.getExpr();
+ Fixups.push_back(MCFixup::Create(0, Expr,
+ MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
+ return 0;
}
unsigned
def simm19_lsl2 : Operand<i32> {
let EncoderMethod = "getSimm19Lsl2Encoding";
let DecoderMethod = "DecodeSimm19Lsl2";
+ let ParserMatchClass = MipsJumpTargetAsmOperand;
}
def simm18_lsl3 : Operand<i32> {
#------------------------------------------------------------------------------
# Check that the assembler can handle the documented syntax for fixups.
#------------------------------------------------------------------------------
+# CHECK-FIXUP: addiupc $2, bar # encoding: [0xec,0b01000AAA,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar@PCREL_LO16,
# CHECK-FIXUP: kind: fixup_MIPS_PCLO16
+# CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
+# CHECK-FIXUP: lwupc $2, bar # encoding: [0xec,0b01010AAA,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
#------------------------------------------------------------------------------
# Check that the appropriate relocations were created.
#------------------------------------------------------------------------------
# CHECK-ELF: Relocations [
-# CHECK-ELF: 0x0 R_MIPS_PC16 bar 0x0
+# CHECK-ELF: 0x0 R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0
-# CHECK-ELF: 0x8 R_MIPS_PC21_S2 bar 0x0
+# CHECK-ELF: 0x8 R_MIPS_PC16 bar 0x0
# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0
-# CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0
+# CHECK-ELF: 0x10 R_MIPS_PC21_S2 bar 0x0
# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0
-# CHECK-ELF: 0x18 R_MIPS_PCHI16 bar 0x0
-# CHECK-ELF: 0x1C R_MIPS_PCLO16 bar 0x0
+# CHECK-ELF: 0x18 R_MIPS_PC26_S2 bar 0x0
+# CHECK-ELF: 0x1C R_MIPS_PCHI16 bar 0x0
+# CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0
+# CHECK-ELF: 0x24 R_MIPS_PC19_S2 bar 0x0
+# CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: ]
+ addiupc $2,bar
beqc $5, $6, bar
bnec $5, $6, bar
beqzc $9, bar
bc bar
aluipc $2, %pcrel_hi(bar)
addiu $2, $2, %pcrel_lo(bar)
+ lwpc $2,bar
+ lwupc $2,bar
#------------------------------------------------------------------------------
# Check that the assembler can handle the documented syntax for fixups.
#------------------------------------------------------------------------------
-# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
+# CHECK-FIXUP: addiupc $2, bar # encoding: [0xec,0b01000AAA,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
+# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16
# CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar@PCREL_LO16,
# CHECK-FIXUP: kind: fixup_MIPS_PCLO16
+# CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
+# CHECK-FIXUP: lwupc $2, bar # encoding: [0xec,0b01010AAA,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
#------------------------------------------------------------------------------
# Check that the appropriate relocations were created.
#------------------------------------------------------------------------------
# CHECK-ELF: Relocations [
-# CHECK-ELF: 0x0 R_MIPS_PC16 bar 0x0
+# CHECK-ELF: 0x0 R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0
-# CHECK-ELF: 0x8 R_MIPS_PC21_S2 bar 0x0
+# CHECK-ELF: 0x8 R_MIPS_PC16 bar 0x0
# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0
-# CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0
+# CHECK-ELF: 0x10 R_MIPS_PC21_S2 bar 0x0
# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0
-# CHECK-ELF: 0x18 R_MIPS_PCHI16 bar 0x0
-# CHECK-ELF: 0x1C R_MIPS_PCLO16 bar 0x0
+# CHECK-ELF: 0x18 R_MIPS_PC26_S2 bar 0x0
+# CHECK-ELF: 0x1C R_MIPS_PCHI16 bar 0x0
+# CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0
+# CHECK-ELF: 0x24 R_MIPS_PC19_S2 bar 0x0
+# CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: ]
+ addiupc $2,bar
beqc $5, $6, bar
bnec $5, $6, bar
beqzc $9, bar
bc bar
aluipc $2, %pcrel_hi(bar)
addiu $2, $2, %pcrel_lo(bar)
+ lwpc $2,bar
+ lwupc $2,bar