Fixed a typo that's causing a missing kill marker.
authorEvan Cheng <evan.cheng@apple.com>
Wed, 12 Sep 2007 23:02:04 +0000 (23:02 +0000)
committerEvan Cheng <evan.cheng@apple.com>
Wed, 12 Sep 2007 23:02:04 +0000 (23:02 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41893 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/LiveVariables.cpp
test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll [new file with mode: 0644]

index 97e8671ca8f5d3a9cb1ea774bbb85f2862fafb7e..dd5afcc432b36c37a8ee439234b8c6335dbcb5d7 100644 (file)
@@ -306,9 +306,8 @@ bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI,
   for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
        unsigned SubReg = *SubRegs; ++SubRegs) {
     MachineInstr *LastRef = PhysRegInfo[SubReg];
-    if (LastRef != RefMI)
-      SubKills.insert(SubReg);
-    else if (!HandlePhysRegKill(SubReg, RefMI, SubKills))
+    if (LastRef != RefMI ||
+        !HandlePhysRegKill(SubReg, RefMI, SubKills))
       SubKills.insert(SubReg);
   }
 
@@ -336,7 +335,7 @@ void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
   SmallSet<unsigned, 4> SubKills;
   if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
-    addRegisterKilled(Reg, RefMI);
+    addRegisterKilled(Reg, RefMI, true);
     return true;
   } else {
     // Some sub-registers are killed by another MI.
diff --git a/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll b/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll
new file mode 100644 (file)
index 0000000..f4b87cf
--- /dev/null
@@ -0,0 +1,15 @@
+; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin
+
+declare void @cxa_atexit_check_1(i8*)
+
+define i32 @check_cxa_atexit(i32 (void (i8*)*, i8*, i8*)* %cxa_atexit, void (i8*)* %cxa_finalize) {
+entry:
+        %tmp7 = call i32 null( void (i8*)* @cxa_atexit_check_1, i8* null, i8* null )            ; <i32> [#uses=0]
+        br i1 false, label %cond_true, label %cond_next
+
+cond_true:    ; preds = %entry
+        ret i32 0
+
+cond_next:        ; preds = %entry
+        ret i32 0
+}