const TargetInstrDesc &TID,
const MachineOperand &MO);
- unsigned getAddrMode1SBit(const MachineInstr &MI,
- const TargetInstrDesc &TID) const;
+ unsigned getAddrModeSBit(const MachineInstr &MI,
+ const TargetInstrDesc &TID) const;
unsigned getAddrMode1InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID,
unsigned getAddrMode4InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID,
unsigned Binary);
+ unsigned getAddrMode6InstrBinary(const MachineInstr &MI,
+ const TargetInstrDesc &TID,
+ unsigned Binary);
/// getInstrBinary - Return binary encoding for the specified
/// machine instruction.
return Binary;
}
-unsigned ARMCodeEmitter::getAddrMode1SBit(const MachineInstr &MI,
- const TargetInstrDesc &TID) const {
+unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
+ const TargetInstrDesc &TID) const {
for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
const MachineOperand &MO = MI.getOperand(i-1);
if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
Binary |= II->getPredicate(&MI) << 28;
// Encode S bit if MI modifies CPSR.
- Binary |= getAddrMode1SBit(MI, TID);
+ Binary |= getAddrModeSBit(MI, TID);
// Encode register def if there is one.
unsigned NumDefs = TID.getNumDefs();
return Binary;
}
+unsigned ARMCodeEmitter::getAddrMode6InstrBinary(const MachineInstr &MI,
+ const TargetInstrDesc &TID,
+ unsigned Binary) {
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << 28;
+
+ // Encode S bit if MI modifies CPSR.
+ Binary |= getAddrModeSBit(MI, TID);
+
+ // 32x32->64bit operations have two destination registers. The number
+ // of register definitions will tell us if that's what we're dealing with.
+ int OpIdx = 0;
+ if (TID.getNumDefs() == 2)
+ Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
+
+ // Encode Rd
+ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
+
+ // Encode Rm
+ Binary |= getMachineOpValue(MI, OpIdx++);
+
+ // Encode Rs
+ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
+
+ return Binary;
+}
+
/// getInstrBinary - Return binary encoding for the specified
/// machine instruction.
unsigned ARMCodeEmitter::getInstrBinary(const MachineInstr &MI) {
return getAddrMode3InstrBinary(MI, TID, Binary);
case ARMII::AddrMode4:
return getAddrMode4InstrBinary(MI, TID, Binary);
+ case ARMII::AddrMode6:
+ return getAddrMode6InstrBinary(MI, TID, Binary);
}
abort();
def AddrMode3 : AddrMode<3>;
def AddrMode4 : AddrMode<4>;
def AddrMode5 : AddrMode<5>;
-def AddrModeT1 : AddrMode<6>;
-def AddrModeT2 : AddrMode<7>;
-def AddrModeT4 : AddrMode<8>;
-def AddrModeTs : AddrMode<9>;
+def AddrMode6 : AddrMode<6>;
+def AddrModeT1 : AddrMode<7>;
+def AddrModeT2 : AddrMode<8>;
+def AddrModeT4 : AddrMode<9>;
+def AddrModeTs : AddrMode<10>;
// Instruction size.
class SizeFlagVal<bits<3> val> {
// Multiply Instructions.
//
-def MUL : AsI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
- "mul", " $dst, $a, $b",
- [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
+def MUL : AsI6<0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
+ "mul", " $dst, $a, $b",
+ [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
-def MLA : AsI<0x2, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
- MulFrm, "mla", " $dst, $a, $b, $c",
- [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
+def MLA : AsI6<0b0010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
+ MulFrm, "mla", " $dst, $a, $b, $c",
+ [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
// Extra precision multiplies with low / high results
-def SMULL : AsI<0xC, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
- MulFrm, "smull", " $ldst, $hdst, $a, $b", []>;
+def SMULL : AsI6<0b1100, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
+ MulFrm, "smull", " $ldst, $hdst, $a, $b", []>;
-def UMULL : AsI<0x8, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
- MulFrm, "umull", " $ldst, $hdst, $a, $b", []>;
+def UMULL : AsI6<0b1000, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
+ MulFrm, "umull", " $ldst, $hdst, $a, $b", []>;
// Multiply + accumulate
-def SMLAL : AsI<0xE, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
- MulFrm, "smlal", " $ldst, $hdst, $a, $b", []>;
+def SMLAL : AsI6<0b1110, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
+ MulFrm, "smlal", " $ldst, $hdst, $a, $b", []>;
-def UMLAL : AsI<0xA, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
- MulFrm, "umlal", " $ldst, $hdst, $a, $b", []>;
+def UMLAL : AsI6<0b1010, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
+ MulFrm, "umlal", " $ldst, $hdst, $a, $b", []>;
-def UMAAL : AI<0x0, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), MulFrm,
- "umaal", " $ldst, $hdst, $a, $b", []>,
- Requires<[IsARM, HasV6]>;
+def UMAAL : AI6 <0b0000, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
+ MulFrm, "umaal", " $ldst, $hdst, $a, $b", []>,
+ Requires<[IsARM, HasV6]>;
// Most significant word multiply
+// FIXME: encoding
def SMMUL : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
"smmul", " $dst, $a, $b",
[(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
Requires<[IsARM, HasV6]>;
+// FIXME: encoding
def SMMLA : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
"smmla", " $dst, $a, $b, $c",
[(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
Requires<[IsARM, HasV6]>;
+// FIXME: encoding
def SMMLS : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
"smmls", " $dst, $a, $b, $c",
[(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
Requires<[IsARM, HasV6]>;
+// FIXME: encoding
multiclass AI_smul<string opc, PatFrag opnode> {
def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
!strconcat(opc, "bb"), " $dst, $a, $b",
}
+// FIXME: encoding
multiclass AI_smla<string opc, PatFrag opnode> {
def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
!strconcat(opc, "bb"), " $dst, $a, $b, $acc",
Requires<[IsARM, HasV5TE]>;
}
+// FIXME: encoding
defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
+// FIXME: encoding
defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
// TODO: Halfword multiple accumulate long: SMLAL<x><y>