Rename a test case to contain correct date info.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209799 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/AArch64/2014-05-16-shrink-v1i64.ll b/test/CodeGen/AArch64/2014-05-16-shrink-v1i64.ll
deleted file mode 100644 (file)
index f31a570..0000000
--- a/test/CodeGen/AArch64/2014-05-16-shrink-v1i64.ll
+++ /dev/null
@@ -1,14 +0,0 @@
-; RUN: llc -march=arm64 < %s
-
-; The DAGCombiner tries to do following shrink:
-;     Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
-; But currently it can't handle vector type and will trigger an assertion failure
-; when it tries to generate an add mixed using vector type and scaler type.
-; This test checks that such assertion failur should not happen.
-define <1 x i64> @dotest(<1 x i64> %in0) {
-entry:
-  %0 = add <1 x i64> %in0, %in0
-  %vshl_n = shl <1 x i64> %0, <i64 32>
-  %vsra_n = ashr <1 x i64> %vshl_n, <i64 32>
-  ret <1 x i64> %vsra_n
-}

diff --git a/test/CodeGen/AArch64/2014-05-29-shrink-v1i64.ll b/test/CodeGen/AArch64/2014-05-29-shrink-v1i64.ll
new file mode 100644 (file)
index 0000000..f31a570
--- /dev/null
+++ b/test/CodeGen/AArch64/2014-05-29-shrink-v1i64.ll
@@ -0,0 +1,14 @@
+; RUN: llc -march=arm64 < %s
+
+; The DAGCombiner tries to do following shrink:
+;     Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
+; But currently it can't handle vector type and will trigger an assertion failure
+; when it tries to generate an add mixed using vector type and scaler type.
+; This test checks that such assertion failur should not happen.
+define <1 x i64> @dotest(<1 x i64> %in0) {
+entry:
+  %0 = add <1 x i64> %in0, %in0
+  %vshl_n = shl <1 x i64> %0, <i64 32>
+  %vsra_n = ashr <1 x i64> %vshl_n, <i64 32>
+  ret <1 x i64> %vsra_n
+}