Fix swapped CASA operands.

Found by SingleSource/UnitTests/AtomicOps.c

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200130 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp
index 85a02edc0a4e24cb523809c3e9df477f7e7280d9..b5550496662920bd48d96c6ba36dedd2ebcbb153 100644 (file)
--- a/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/lib/Target/Sparc/SparcISelLowering.cpp
@@ -2977,7 +2977,7 @@ SparcTargetLowering::expandAtomicRMW(MachineInstr *MI,
   // loop:
   //   %val = phi %val0, %dest
   //   %upd = op %val, %rs2
-  //   %dest = cas %addr, %upd, %val
+  //   %dest = cas %addr, %val, %upd
   //   cmp %val, %dest
   //   bne loop
   // done:
@@ -3036,7 +3036,7 @@ SparcTargetLowering::expandAtomicRMW(MachineInstr *MI,
   }
 
   BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg)
-    .addReg(AddrReg).addReg(UpdReg).addReg(ValReg)
+    .addReg(AddrReg).addReg(ValReg).addReg(UpdReg)
     .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
   BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg);
   BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND))

diff --git a/test/CodeGen/SPARC/atomics.ll b/test/CodeGen/SPARC/atomics.ll
index 3d0be28accd28404fedbea0b4c1aab1af6dd3a56..6d2b48287ca58cae28e9118dfe6b3e88aaa7727b 100644 (file)
--- a/test/CodeGen/SPARC/atomics.ll
+++ b/test/CodeGen/SPARC/atomics.ll
@@ -64,8 +64,8 @@ entry:
 
 ; CHECK-LABEL: test_load_add_32
 ; CHECK: membar
-; CHECK: add
-; CHECK: cas [%o0]
+; CHECK: add [[V:%[gilo][0-7]]], %o1, [[U:%[gilo][0-7]]]
+; CHECK: cas [%o0], [[V]], [[U]]
 ; CHECK: membar
 define zeroext i32 @test_load_add_32(i32* %p, i32 zeroext %v) {
 entry: