[ARM64-BE] Correct grammar mistake pointed out by Tobias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208580 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/docs/BigEndianNEON.rst b/docs/BigEndianNEON.rst
index ef905bf816d2d021985eeba049429029c1c78443..4dc1628a0ea1b3f99fa112ef4992d327a7d5c7c0 100644 (file)
--- a/docs/BigEndianNEON.rst
+++ b/docs/BigEndianNEON.rst
@@ -90,7 +90,7 @@ Considerations
 LLVM IR Lane ordering
 ---------------------
 
-LLVM IR has first class vector types. In LLVM IR, the zero'th element of a vector resides at the lowest memory address. The optimizer relies on this property in certain areas, for example when concatenating vectors together. The intention is for arrays and vectors to have identical memory layouts - ``[4 x i8]`` and ``<4 x i8>`` should be represented the same in memory. Without this property there would be many special cases that the optimizer would have the cleverly handle.
+LLVM IR has first class vector types. In LLVM IR, the zero'th element of a vector resides at the lowest memory address. The optimizer relies on this property in certain areas, for example when concatenating vectors together. The intention is for arrays and vectors to have identical memory layouts - ``[4 x i8]`` and ``<4 x i8>`` should be represented the same in memory. Without this property there would be many special cases that the optimizer would have to cleverly handle.
 
 Use of ``LDR`` would break this lane ordering property. This doesn't preclude the use of ``LDR``, but we would have to do one of two things: