Fix problems with empty basic blocks

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5326 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index 57690e9c761068f3afeeb0771489cf6d7bb7a0f2..1bb6332c6e4be24afdcb5c2851da1cbfdaf77420 100644 (file)
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -50,7 +50,7 @@ const PassInfo *PHIEliminationID = X.getPassInfo();
 /// predecessor basic blocks.
 ///
 bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
-  if (MBB.front()->getOpcode() != TargetInstrInfo::PHI)
+  if (MBB.empty() || MBB.front()->getOpcode() != TargetInstrInfo::PHI)
     return false;   // Quick exit for normal case...
 
   LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
@@ -76,7 +76,8 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
     // into the phi node destination.
     //
     MachineBasicBlock::iterator AfterPHIsIt = MBB.begin();
-    while ((*AfterPHIsIt)->getOpcode() == TargetInstrInfo::PHI) ++AfterPHIsIt;
+    if (AfterPHIsIt != MBB.end())
+      while ((*AfterPHIsIt)->getOpcode() == TargetInstrInfo::PHI) ++AfterPHIsIt;
     RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC);
 
     // Add information to LiveVariables to know that the incoming value is dead
@@ -108,16 +109,19 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
         }
 
       if (HaveNotEmitted) {
-        MachineBasicBlock::iterator I = opBlock.end()-1;
-        
-        // must backtrack over ALL the branches in the previous block
-        while (MII.isTerminatorInstr((*I)->getOpcode()) && I != opBlock.begin())
+        MachineBasicBlock::iterator I = opBlock.end();
+        if (I != opBlock.begin()) {  // Handle empty blocks
           --I;
+          // must backtrack over ALL the branches in the previous block
+          while (MII.isTerminatorInstr((*I)->getOpcode()) &&
+                 I != opBlock.begin())
+            --I;
         
-        // move back to the first branch instruction so new instructions
-        // are inserted right in front of it and not in front of a non-branch
-        if (!MII.isTerminatorInstr((*I)->getOpcode()))
-          ++I;
+          // move back to the first branch instruction so new instructions
+          // are inserted right in front of it and not in front of a non-branch
+          if (!MII.isTerminatorInstr((*I)->getOpcode()))
+            ++I;
+        }
 
        assert(opVal.isVirtualRegister() &&
               "Machine PHI Operands must all be virtual registers!");

diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index 8fd2375a1fa530c300d2bef2b4840a939c08753d..2f7f1f4ef30a8e49a595edf2f7d77333828912e0 100644 (file)
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -221,7 +221,7 @@ void PEI::insertPrologEpilogCode(MachineFunction &Fn) {
   const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
   for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
     // If last instruction is a return instruction, add an epilogue
-    if (TII.isReturn(I->back()->getOpcode()))
+    if (!I->empty() && TII.isReturn(I->back()->getOpcode()))
       Fn.getTarget().getRegisterInfo()->emitEpilogue(Fn, *I);
   }
 }

diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index d6e273a8a680ae048cd9afd58841126d88adf9e6..46b06ce04402c65b23e8ec521f0378b633bdee4a 100644 (file)
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -572,7 +572,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
 
   // Rewind the iterator to point to the first flow control instruction...
   const TargetInstrInfo &TII = TM->getInstrInfo();
-  I = MBB.end()-1;
+  I = MBB.end();
   while (I != MBB.begin() && TII.isTerminatorInstr((*(I-1))->getOpcode()))
     --I;