Remove non-DebugLoc versions of BuildMI from Alpha and Cell.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64433 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index e4d3ecdff9aa26965e5486afb266aaad26404c77..10011125cf852f5ab48d5dcfaddb9f1d589ec8fa 100644 (file)
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -728,6 +728,7 @@ AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
   //test sc and maybe branck to start
   //exit:
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
+  DebugLoc dl = MI->getDebugLoc();
   MachineFunction::iterator It = BB;
   ++It;
   
@@ -741,46 +742,46 @@ AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
   F->insert(It, llscMBB);
   F->insert(It, sinkMBB);
 
-  BuildMI(thisMBB, TII->get(Alpha::BR)).addMBB(llscMBB);
+  BuildMI(thisMBB, dl, TII->get(Alpha::BR)).addMBB(llscMBB);
   
   unsigned reg_res = MI->getOperand(0).getReg(),
     reg_ptr = MI->getOperand(1).getReg(),
     reg_v2 = MI->getOperand(2).getReg(),
     reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
 
-  BuildMI(llscMBB, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L), 
+  BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L), 
           reg_res).addImm(0).addReg(reg_ptr);
   switch (MI->getOpcode()) {
   case Alpha::CAS32:
   case Alpha::CAS64: {
     unsigned reg_cmp 
       = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
-    BuildMI(llscMBB, TII->get(Alpha::CMPEQ), reg_cmp)
+    BuildMI(llscMBB, dl, TII->get(Alpha::CMPEQ), reg_cmp)
       .addReg(reg_v2).addReg(reg_res);
-    BuildMI(llscMBB, TII->get(Alpha::BEQ))
+    BuildMI(llscMBB, dl, TII->get(Alpha::BEQ))
       .addImm(0).addReg(reg_cmp).addMBB(sinkMBB);
-    BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store)
+    BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store)
       .addReg(Alpha::R31).addReg(MI->getOperand(3).getReg());
     break;
   }
   case Alpha::LAS32:
   case Alpha::LAS64: {
-    BuildMI(llscMBB, TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store)
+    BuildMI(llscMBB, dl,TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store)
       .addReg(reg_res).addReg(reg_v2);
     break;
   }
   case Alpha::SWAP32:
   case Alpha::SWAP64: {
-    BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store)
+    BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store)
       .addReg(reg_v2).addReg(reg_v2);
     break;
   }
   }
-  BuildMI(llscMBB, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store)
+  BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store)
     .addReg(reg_store).addImm(0).addReg(reg_ptr);
-  BuildMI(llscMBB, TII->get(Alpha::BEQ))
+  BuildMI(llscMBB, dl, TII->get(Alpha::BEQ))
     .addImm(0).addReg(reg_store).addMBB(llscMBB);
-  BuildMI(llscMBB, TII->get(Alpha::BR)).addMBB(sinkMBB);
+  BuildMI(llscMBB, dl, TII->get(Alpha::BR)).addMBB(sinkMBB);
 
   thisMBB->addSuccessor(llscMBB);
   llscMBB->addSuccessor(llscMBB);

diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index 42dc44802128cf49af1d2effdf60f309cdd1cbbd..73e9b7b2d57109fd551ff848b394bfc21d515a62 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -108,6 +108,8 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
                                       MachineBasicBlock *TBB,
                                       MachineBasicBlock *FBB,
                             const SmallVectorImpl<MachineOperand> &Cond) const {
+  // FIXME this should probably have a DebugLoc argument
+  DebugLoc dl = DebugLoc::getUnknownLoc();
   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
   assert((Cond.size() == 2 || Cond.size() == 0) && 
          "Alpha branch conditions have two components!");
@@ -115,25 +117,25 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
   // One-way branch.
   if (FBB == 0) {
     if (Cond.empty())   // Unconditional branch
-      BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB);
+      BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB);
     else                // Conditional branch
       if (isAlphaIntCondCode(Cond[0].getImm()))
-        BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
+        BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
           .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
       else
-        BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
+        BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
           .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
     return 1;
   }
   
   // Two-way Conditional Branch.
   if (isAlphaIntCondCode(Cond[0].getImm()))
-    BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
+    BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
       .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
   else
-    BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
+    BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
       .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
-  BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB);
+  BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB);
   return 2;
 }
 

diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp
index 7a1b78497b829775e7a83ee2b3d0327faf37bb3e..0c51bc554be949e8d2893577a3a1acf436115f11 100644 (file)
--- a/lib/Target/Alpha/AlphaLLRP.cpp
+++ b/lib/Target/Alpha/AlphaLLRP.cpp
@@ -49,6 +49,7 @@ namespace {
       const TargetInstrInfo *TII = F.getTarget().getInstrInfo();
       bool Changed = false;
       MachineInstr* prev[3] = {0,0,0};
+      DebugLoc dl = DebugLoc::getUnknownLoc();
       unsigned count = 0;
       for (MachineFunction::iterator FI = F.begin(), FE = F.end();
            FI != FE; ++FI) {
@@ -73,7 +74,7 @@ namespace {
                prev[0] = prev[1];
                prev[1] = prev[2];
                prev[2] = 0;
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
                  .addReg(Alpha::R31)
                  .addReg(Alpha::R31); 
                Changed = true; nopintro += 1;
@@ -85,10 +86,10 @@ namespace {
                         MI->getOperand(1).getImm()) {
                prev[0] = prev[2];
                prev[1] = prev[2] = 0;
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
                  .addReg(Alpha::R31)
                  .addReg(Alpha::R31); 
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
                  .addReg(Alpha::R31)
                  .addReg(Alpha::R31);
                Changed = true; nopintro += 2;
@@ -99,12 +100,12 @@ namespace {
                         && prev[2]->getOperand(1).getImm() == 
                         MI->getOperand(1).getImm()) {
                prev[0] = prev[1] = prev[2] = 0;
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                 .addReg(Alpha::R31);
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                 .addReg(Alpha::R31);
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                 .addReg(Alpha::R31);
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31).addReg(Alpha::R31);
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31).addReg(Alpha::R31);
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31).addReg(Alpha::R31);
                Changed = true; nopintro += 3;
                count += 3;
              }
@@ -136,7 +137,7 @@ namespace {
         if (ub || AlignAll) {
           //we can align stuff for free at this point
           while (count % 4) {
-            BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
+            BuildMI(MBB, MBB.end(), dl, TII->get(Alpha::BISr), Alpha::R31)
               .addReg(Alpha::R31).addReg(Alpha::R31);
             ++count;
             ++nopalign;

diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index a0b6e09c50a8e3c4e2ff453bafc96e959cc0ed8e..2ed8dac16a16bf26acb2afe579ca33a14648bce4 100644 (file)
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -202,20 +202,21 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
   MachineBasicBlock::iterator MBBI = MBB.begin();
   MachineFrameInfo *MFI = MF.getFrameInfo();
+  DebugLoc dl = DebugLoc::getUnknownLoc();
   bool FP = hasFP(MF);
 
   static int curgpdist = 0;
 
   //handle GOP offset
-  BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29)
+  BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29)
     .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
     .addReg(Alpha::R27).addImm(++curgpdist);
-  BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29)
+  BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29)
     .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
     .addReg(Alpha::R29).addImm(curgpdist);
 
   //evil const_cast until MO stuff setup to handle const
-  BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT))
+  BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT))
     .addGlobalAddress(const_cast<Function*>(MF.getFunction()));
 
   // Get the number of bytes to allocate from the FrameInfo
@@ -236,13 +237,13 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
   // adjust stack pointer: r30 -= numbytes
   NumBytes = -NumBytes;
   if (NumBytes >= IMM_LOW) {
-    BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
+    BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
       .addReg(Alpha::R30);
   } else if (getUpper16(NumBytes) >= IMM_LOW) {
-    BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes))
-      .addReg(Alpha::R30);
-    BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes))
-      .addReg(Alpha::R30);
+    BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30)
+      .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
+    BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30)
+      .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
   } else {
     cerr << "Too big a stack frame at " << NumBytes << "\n";
     abort();
@@ -251,10 +252,10 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
   //now if we need to, save the old FP and set the new
   if (FP)
   {
-    BuildMI(MBB, MBBI, TII.get(Alpha::STQ))
+    BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ))
       .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
     //this must be the last instr in the prolog
-    BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15)
+    BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15)
       .addReg(Alpha::R30).addReg(Alpha::R30);
   }
 
@@ -267,6 +268,7 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
   assert((MBBI->getOpcode() == Alpha::RETDAG ||
           MBBI->getOpcode() == Alpha::RETDAGp)
          && "Can only insert epilog into returning blocks");
+  DebugLoc dl = DebugLoc::getUnknownLoc();
 
   bool FP = hasFP(MF);
 
@@ -276,20 +278,21 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
   //now if we need to, restore the old FP
   if (FP) {
     //copy the FP into the SP (discards allocas)
-    BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
+    BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
       .addReg(Alpha::R15);
     //restore the FP
-    BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15);
+    BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15)
+      .addImm(0).addReg(Alpha::R15);
   }
 
   if (NumBytes != 0) {
     if (NumBytes <= IMM_HIGH) {
-      BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
+      BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
         .addReg(Alpha::R30);
     } else if (getUpper16(NumBytes) <= IMM_HIGH) {
-      BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30)
+      BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30)
         .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
-      BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30)
+      BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30)
         .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
     } else {
       cerr << "Too big a stack frame at " << NumBytes << "\n";

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index d2ec7b1a1e42c8588d4c2b8d7fee75bf3085a1d5..439daaea3c283dbaafc898a0106cf3b0fae1e6b2 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -627,6 +627,8 @@ unsigned
 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                            MachineBasicBlock *FBB,
                            const SmallVectorImpl<MachineOperand> &Cond) const {
+  // FIXME this should probably have a DebugLoc argument
+  DebugLoc dl = DebugLoc::getUnknownLoc();
   // Shouldn't be a fall through.
   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
   assert((Cond.size() == 2 || Cond.size() == 0) &&
@@ -636,14 +638,14 @@ SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
   if (FBB == 0) {
     if (Cond.empty()) {
       // Unconditional branch
-      MachineInstrBuilder MIB = BuildMI(&MBB, get(SPU::BR));
+      MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(SPU::BR));
       MIB.addMBB(TBB);
 
       DEBUG(cerr << "Inserted one-way uncond branch: ");
       DEBUG((*MIB).dump());
     } else {
       // Conditional branch
-      MachineInstrBuilder  MIB = BuildMI(&MBB, get(Cond[0].getImm()));
+      MachineInstrBuilder  MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
       MIB.addReg(Cond[1].getReg()).addMBB(TBB);
 
       DEBUG(cerr << "Inserted one-way cond branch:   ");
@@ -651,8 +653,8 @@ SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
     }
     return 1;
   } else {
-    MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm()));
-    MachineInstrBuilder MIB2 = BuildMI(&MBB, get(SPU::BR));
+    MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
+    MachineInstrBuilder MIB2 = BuildMI(&MBB, dl, get(SPU::BR));
 
     // Two-way Conditional Branch.
     MIB.addReg(Cond[1].getReg()).addMBB(TBB);

diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp
index 030a7d7600dfee31a533af43be96f847d1f8b413..64ed8287972ac5fdb544efa04bdef02902dbd8c2 100644 (file)
--- a/lib/Target/CellSPU/SPURegisterInfo.cpp
+++ b/lib/Target/CellSPU/SPURegisterInfo.cpp
@@ -428,6 +428,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
   MachineBasicBlock::iterator MBBI = MBB.begin();
   MachineFrameInfo *MFI = MF.getFrameInfo();
   MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
+  DebugLoc dl = DebugLoc::getUnknownLoc();
 
   // Prepare for debug frame info.
   bool hasDebugInfo = MMI && MMI->hasDebugInfo();
@@ -448,38 +449,38 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
     if (hasDebugInfo) {
       // Mark effective beginning of when frame pointer becomes valid.
       FrameLabelId = MMI->NextLabelID();
-      BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(FrameLabelId);
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(FrameLabelId);
     }
 
     // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
     // for the ABI
-    BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
+    BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
       .addReg(SPU::R1);
     if (isS10Constant(FrameSize)) {
       // Spill $sp to adjusted $sp
-      BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
         .addReg(SPU::R1);
       // Adjust $sp by required amout
-      BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
         .addImm(FrameSize);
     } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
       // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
       // $r2 to adjust $sp:
-      BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
         .addImm(-16)
         .addReg(SPU::R1);
-      BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
         .addImm(FrameSize);
-      BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1)
         .addReg(SPU::R2)
         .addReg(SPU::R1);
-      BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
         .addReg(SPU::R1)
         .addReg(SPU::R2);
-      BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2)
         .addReg(SPU::R2)
         .addImm(16);
-      BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2)
         .addReg(SPU::R2)
         .addReg(SPU::R1);
     } else {
@@ -508,7 +509,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
 
       // Mark effective beginning of when frame pointer is ready.
       unsigned ReadyLabelId = MMI->NextLabelID();
-      BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(ReadyLabelId);
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(ReadyLabelId);
 
       MachineLocation FPDst(SPU::R1);
       MachineLocation FPSrc(MachineLocation::VirtualFP);
@@ -522,7 +523,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
       MachineBasicBlock::iterator MBBI = prior(MBB.end());
       // Insert terminator label
       unsigned BranchLabelId = MMI->NextLabelID();
-      BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(BranchLabelId);
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(BranchLabelId);
     }
   }
 }
@@ -534,6 +535,7 @@ SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
   const MachineFrameInfo *MFI = MF.getFrameInfo();
   int FrameSize = MFI->getStackSize();
   int LinkSlotOffset = SPUFrameInfo::stackSlotSize();
+  DebugLoc dl = DebugLoc::getUnknownLoc();
 
   assert(MBBI->getOpcode() == SPU::RET &&
          "Can only insert epilog into returning blocks");
@@ -545,30 +547,30 @@ SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
       // Reload $lr, adjust $sp by required amount
       // Note: We do this to slightly improve dual issue -- not by much, but it
       // is an opportunity for dual issue.
-      BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
         .addImm(FrameSize + LinkSlotOffset)
         .addReg(SPU::R1);
-      BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1)
         .addReg(SPU::R1)
         .addImm(FrameSize);
     } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
       // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
       // $r2 to adjust $sp:
-      BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
         .addImm(16)
         .addReg(SPU::R1);
-      BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
         .addImm(FrameSize);
-      BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
         .addReg(SPU::R1)
         .addReg(SPU::R2);
-      BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
         .addImm(16)
         .addReg(SPU::R2);
-      BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2).
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2).
         addReg(SPU::R2)
         .addImm(16);
-      BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2)
+      BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2)
         .addReg(SPU::R2)
         .addReg(SPU::R1);
     } else {