git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255816
91177308-0d34-0410-b5e6-
96231b3b80d8
//===----------------------------------------------------------------------===//
MVT WebAssemblyAsmPrinter::getRegType(unsigned RegNo) const {
//===----------------------------------------------------------------------===//
MVT WebAssemblyAsmPrinter::getRegType(unsigned RegNo) const {
- const TargetRegisterClass *TRC = MRI->getRegClass(RegNo);
+ const TargetRegisterClass *TRC =
+ TargetRegisterInfo::isVirtualRegister(RegNo) ?
+ MRI->getRegClass(RegNo) :
+ MRI->getTargetRegisterInfo()->getMinimalPhysRegClass(RegNo);
for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
if (TRC->hasType(T))
return T;
for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
if (TRC->hasType(T))
return T;
Local.addOperand(MCOperand::createImm(getRegType(VReg).SimpleTy));
AnyWARegs = true;
}
Local.addOperand(MCOperand::createImm(getRegType(VReg).SimpleTy));
AnyWARegs = true;
}
- if (MF->getFrameInfo()->getStackSize() > 0) {
- // TODO: wasm64
- Local.addOperand(MCOperand::createImm(MVT::i32));
+ auto &PhysRegs = MFI->getPhysRegs();
+ for (unsigned PReg = 0; PReg < PhysRegs.size(); ++PReg) {
+ if (PhysRegs[PReg] == -1U)
+ continue;
+ Local.addOperand(MCOperand::createImm(getRegType(PReg).SimpleTy));
AnyWARegs = true;
}
if (AnyWARegs)
AnyWARegs = true;
}
if (AnyWARegs)
assert(WAReg < -1U);
PhysRegs[PReg] = WAReg;
}
assert(WAReg < -1U);
PhysRegs[PReg] = WAReg;
}
+ const std::vector<unsigned> &getPhysRegs() const { return PhysRegs; }
};
} // end namespace llvm
};
} // end namespace llvm