void MarkVirtRegAliveInBlock(VarInfo &VRInfo, MachineBasicBlock *BB);
void HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
- MachineInstr *MI);
+ MachineInstr *MI);
};
} // End llvm namespace
void removeNodeFromList(MachineBasicBlock* N);
void transferNodesFromList(iplist<MachineBasicBlock,
ilist_traits<MachineBasicBlock> > &toList,
- ilist_iterator<MachineBasicBlock> first,
- ilist_iterator<MachineBasicBlock> last);
+ ilist_iterator<MachineBasicBlock> first,
+ ilist_iterator<MachineBasicBlock> last);
};
/// MachineFunctionInfo - This class can be derived from and used by targets to
// first and initialize each one later.
//
// E.g, for this VM instruction:
-// ptr = alloca type, numElements
+// ptr = alloca type, numElements
// we generate 2 machine instructions on the SPARC:
//
-// mul Constant, Numelements -> Reg
-// add %sp, Reg -> Ptr
+// mul Constant, Numelements -> Reg
+// add %sp, Reg -> Ptr
//
// Each instruction has 3 operands, listed above. Of those:
-// - Reg, NumElements, and Ptr are of operand type MO_Register.
-// - Constant is of operand type MO_SignExtendedImmed on the SPARC.
-//
+// - Reg, NumElements, and Ptr are of operand type MO_Register.
+// - Constant is of operand type MO_SignExtendedImmed on the SPARC.
+//
// For the register operands, the virtual register type is as follows:
-//
-// - Reg will be of virtual register type MO_MInstrVirtualReg. The field
-// MachineInstr* minstr will point to the instruction that computes reg.
//
-// - %sp will be of virtual register type MO_MachineReg.
-// The field regNum identifies the machine register.
+// - Reg will be of virtual register type MO_MInstrVirtualReg. The field
+// MachineInstr* minstr will point to the instruction that computes reg.
+//
+// - %sp will be of virtual register type MO_MachineReg.
+// The field regNum identifies the machine register.
//
-// - NumElements will be of virtual register type MO_VirtualReg.
-// The field Value* value identifies the value.
+// - NumElements will be of virtual register type MO_VirtualReg.
+// The field Value* value identifies the value.
//
-// - Ptr will also be of virtual register type MO_VirtualReg.
-// Again, the field Value* value identifies the value.
+// - Ptr will also be of virtual register type MO_VirtualReg.
+// Again, the field Value* value identifies the value.
//
//===----------------------------------------------------------------------===//
};
enum MachineOperandType {
- MO_VirtualRegister, // virtual register for *value
- MO_MachineRegister, // pre-assigned machine register `regNum'
+ MO_VirtualRegister, // virtual register for *value
+ MO_MachineRegister, // pre-assigned machine register `regNum'
MO_CCRegister,
MO_SignExtendedImmed,
MO_UnextendedImmed,
// the generated machine code.
// LLVM global for MO_GlobalAddress.
- int64_t immedVal; // Constant value for an explicit constant
+ int64_t immedVal; // Constant value for an explicit constant
MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
const char *SymbolName; // For MO_ExternalSymbol type
char flags; // see bit field definitions above
MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
union {
- int regNum; // register number for an explicit register
+ int regNum; // register number for an explicit register
// will be set for a value after reg allocation
int offset; // Offset to address of global or external, only
}
MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy,
- bool isPCRelative = false)
+ bool isPCRelative = false)
: flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) {
assert(OpTy != MachineOperand::MO_GlobalAddress);
zeroContents();
}
MachineOperand(GlobalValue *V, MachineOperandType OpTy, UseType UseTy,
- bool isPCRelative = false, int Offset = 0)
+ bool isPCRelative = false, int Offset = 0)
: flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) {
assert(OpTy == MachineOperand::MO_GlobalAddress);
zeroContents ();
///
void setRegForValue(int reg) {
assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
- opType == MO_MachineRegister);
+ opType == MO_MachineRegister);
extra.regNum = reg;
}
// Iterators
iterator beginInEdges() { return inEdges.begin(); }
- iterator endInEdges() { return inEdges.end(); }
+ iterator endInEdges() { return inEdges.end(); }
iterator beginOutEdges() { return outEdges.begin(); }
iterator endOutEdges() { return outEdges.end(); }
protected:
friend class SchedGraphCommon;
- friend class SchedGraphEdge; // give access for adding edges
+ friend class SchedGraphEdge; // give access for adding edges
// disable default constructor and provide a ctor for single-block graphs
- SchedGraphNodeCommon(); // DO NOT IMPLEMENT
+ SchedGraphNodeCommon(); // DO NOT IMPLEMENT
inline SchedGraphNodeCommon(unsigned Id, int index, int late=0) : ID(Id), latency(late), origIndexInBB(index) {}
// ostream << operator for SchedGraphNode class
inline std::ostream &operator<<(std::ostream &os,
- const SchedGraphNodeCommon &node) {
+ const SchedGraphNodeCommon &node) {
node.print(os);
return os;
}
};
protected:
- SchedGraphNodeCommon* src;
- SchedGraphNodeCommon* sink;
+ SchedGraphNodeCommon* src;
+ SchedGraphNodeCommon* sink;
SchedGraphEdgeDepType depType;
unsigned int depOrderType;
int minDelay; // cached latency (assumes fixed target arch)
ResourceId resourceId;
};
-public:
+public:
// For all constructors, if minDelay is unspecified, minDelay is
// set to _src->getLatency().
// constructor for CtrlDep or MemoryDep edges, selected by 3rd argument
SchedGraphEdge(SchedGraphNodeCommon* _src, SchedGraphNodeCommon* _sink,
- SchedGraphEdgeDepType _depType, unsigned int _depOrderType,
- int _minDelay = -1);
+ SchedGraphEdgeDepType _depType, unsigned int _depOrderType,
+ int _minDelay = -1);
// constructor for explicit value dependence (may be true/anti/output)
SchedGraphEdge(SchedGraphNodeCommon* _src, SchedGraphNodeCommon* _sink,
- const Value* _val, unsigned int _depOrderType,
- int _minDelay = -1);
+ const Value* _val, unsigned int _depOrderType,
+ int _minDelay = -1);
// constructor for machine register dependence
SchedGraphEdge(SchedGraphNodeCommon* _src,SchedGraphNodeCommon* _sink,
- unsigned int _regNum, unsigned int _depOrderType,
- int _minDelay = -1);
+ unsigned int _regNum, unsigned int _depOrderType,
+ int _minDelay = -1);
// constructor for any other machine resource dependences.
// DataDepOrderType is always NonDataDep. It it not an argument to
// avoid overloading ambiguity with previous constructor.
SchedGraphEdge(SchedGraphNodeCommon* _src, SchedGraphNodeCommon* _sink,
- ResourceId _resourceId, int _minDelay = -1);
+ ResourceId _resourceId, int _minDelay = -1);
~SchedGraphEdge() {}
- SchedGraphNodeCommon* getSrc() const { return src; }
- SchedGraphNodeCommon* getSink() const { return sink; }
+ SchedGraphNodeCommon* getSrc() const { return src; }
+ SchedGraphNodeCommon* getSink() const { return sink; }
int getMinDelay() const { return minDelay; }
SchedGraphEdgeDepType getDepType() const { return depType; }
unsigned int getDepOrderType() const { return depOrderType; }
private:
// disable default ctor
- SchedGraphEdge(); // DO NOT IMPLEMENT
+ SchedGraphEdge(); // DO NOT IMPLEMENT
};
// ostream << operator for SchedGraphNode class
inline _EdgeType* getEdge() const { return *(oi); }
inline _Self &operator++() { ++oi; return *this; } // Preincrement
- inline _Self operator++(int) { // Postincrement
+ inline _Self operator++(int) { // Postincrement
_Self tmp(*this); ++*this; return tmp;
}
inline _Self &operator--() { --oi; return *this; } // Predecrement
- inline _Self operator--(int) { // Postdecrement
+ inline _Self operator--(int) { // Postdecrement
_Self tmp = *this; --*this; return tmp;
}
};
inline _EdgeType* getEdge() const { return *(oi); }
inline _Self &operator++() { ++oi; return *this; } // Preincrement
- inline _Self operator++(int) { // Postincrement
+ inline _Self operator++(int) { // Postincrement
_Self tmp(*this); ++*this; return tmp;
}
inline _Self &operator--() { --oi; return *this; } // Predecrement
- inline _Self operator--(int) { // Postdecrement
+ inline _Self operator--(int) { // Postdecrement
_Self tmp = *this; --*this; return tmp;
}
};
******************************************************************************
*
* Description:
- * This header file includes the infamous alloc.h header file if the
- * autoconf system has found it. It hides all of the autoconf details
- * from the rest of the application source code.
+ * This header file includes the infamous alloc.h header file if the
+ * autoconf system has found it. It hides all of the autoconf details
+ * from the rest of the application source code.
*/
#ifndef _CONFIG_ALLOC_H
/*
* This is a modified version of that suggested by the Autoconf manual.
- * 1) The #pragma is indented so that pre-ANSI C compilers ignore it.
- * 2) If alloca.h cannot be found, then try stdlib.h. Some platforms
- * (notably FreeBSD) defined alloca() there.
+ * 1) The #pragma is indented so that pre-ANSI C compilers ignore it.
+ * 2) If alloca.h cannot be found, then try stdlib.h. Some platforms
+ * (notably FreeBSD) defined alloca() there.
*/
#ifdef _MSC_VER
#include <malloc.h>
#elif defined(__MINGW32__) && defined(HAVE_MALLOC_H)
#include <malloc.h>
#elif !defined(__GNUC__)
-# ifdef _AIX
- # pragma alloca
-# else
-# ifndef alloca
- char * alloca ();
-# endif
-# endif
+# ifdef _AIX
+# pragma alloca
+# else
+# ifndef alloca
+ char * alloca ();
+# endif
+# endif
#else
-# ifdef HAVE_STDLIB_H
-# include <stdlib.h>
-# else
-# error "The function alloca() is required but not found!"
-# endif
+# ifdef HAVE_STDLIB_H
+# include <stdlib.h>
+# else
+# error "The function alloca() is required but not found!"
+# endif
#endif
#endif
protected:
MRegisterInfo(const MRegisterDesc *D, unsigned NR,
regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
- int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
+ int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
virtual ~MRegisterInfo();
public:
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
- "eliminateCallFramePseudoInstr must be implemented if using"
- " call frame setup/destroy pseudo instructions!");
+ "eliminateCallFramePseudoInstr must be implemented if using"
+ " call frame setup/destroy pseudo instructions!");
assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
}
// This method adjusts a stack offset to meet alignment rules of target.
virtual int adjustAlignment(int unalignedOffset, bool growUp,
- unsigned align) const;
+ unsigned align) const;
// These methods compute offsets using the frame contents for a particular
// function. The frame contents are obtained from the MachineFunction object
// for the given function. The rest must be implemented by the
// machine-specific subclass.
//
- virtual int getIncomingArgOffset (MachineFunction& mcInfo,
- unsigned argNum) const;
- virtual int getOutgoingArgOffset (MachineFunction& mcInfo,
- unsigned argNum) const;
-
- virtual int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
- bool& growUp) const;
- virtual int getRegSpillAreaOffset (MachineFunction& mcInfo,
- bool& growUp) const;
- virtual int getTmpAreaOffset (MachineFunction& mcInfo,
- bool& growUp) const;
- virtual int getDynamicAreaOffset (MachineFunction& mcInfo,
- bool& growUp) const;
+ virtual int getIncomingArgOffset(MachineFunction& mcInfo,
+ unsigned argNum) const;
+ virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
+ unsigned argNum) const;
+ virtual int getFirstAutomaticVarOffset(MachineFunction& mcInfo,
+ bool& growUp) const;
+ virtual int getRegSpillAreaOffset(MachineFunction& mcInfo,
+ bool& growUp) const;
+ virtual int getTmpAreaOffset(MachineFunction& mcInfo, bool& growUp) const;
+ virtual int getDynamicAreaOffset(MachineFunction& mcInfo, bool& growUp) const;
};
} // End llvm namespace
//---------------------------------------------------------------------------
// struct TargetInstrDescriptor:
-// Predefined information about each machine instruction.
-// Designed to initialized statically.
+// Predefined information about each machine instruction.
+// Designed to initialized statically.
//
-const unsigned M_NOP_FLAG = 1 << 0;
-const unsigned M_BRANCH_FLAG = 1 << 1;
-const unsigned M_CALL_FLAG = 1 << 2;
-const unsigned M_RET_FLAG = 1 << 3;
-const unsigned M_BARRIER_FLAG = 1 << 4;
-const unsigned M_DELAY_SLOT_FLAG = 1 << 5;
-const unsigned M_CC_FLAG = 1 << 6;
-const unsigned M_LOAD_FLAG = 1 << 7;
-const unsigned M_STORE_FLAG = 1 << 8;
+const unsigned M_NOP_FLAG = 1 << 0;
+const unsigned M_BRANCH_FLAG = 1 << 1;
+const unsigned M_CALL_FLAG = 1 << 2;
+const unsigned M_RET_FLAG = 1 << 3;
+const unsigned M_BARRIER_FLAG = 1 << 4;
+const unsigned M_DELAY_SLOT_FLAG = 1 << 5;
+const unsigned M_CC_FLAG = 1 << 6;
+const unsigned M_LOAD_FLAG = 1 << 7;
+const unsigned M_STORE_FLAG = 1 << 8;
// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones.
-const unsigned M_2_ADDR_FLAG = 1 << 9;
+const unsigned M_2_ADDR_FLAG = 1 << 9;
// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be
// changed into a 3-address instruction if the first two operands cannot be
int numOperands; // Number of args; -1 if variable #args
int resultPos; // Position of the result; -1 if no result
unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0.
- bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
+ bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
// smallest -ve value is -(maxImmedConst+1).
unsigned numDelaySlots; // Number of delay slots after instruction
unsigned latency; // Latency in machine cycles
// of this machine instruction
//
virtual bool constantFitsInImmedField(MachineOpCode Opcode,
- int64_t intValue) const;
+ int64_t intValue) const;
// Return the largest positive constant that can be held in the IMMED field
// of this machine instruction.
// Return 0 if the instruction has no IMMED field.
//
virtual uint64_t maxImmedConstant(MachineOpCode Opcode,
- bool &isSignExtended) const {
+ bool &isSignExtended) const {
isSignExtended = get(Opcode).immedIsSignExtended;
return get(Opcode).maxImmedConst;
}
struct InstrClassRUsage {
InstrSchedClass schedClass;
- int totCycles;
+ int totCycles;
// Issue restrictions common to instructions in this class
unsigned maxNumIssue;
- bool isSingleIssue;
- bool breaksGroup;
- CycleCount_t numBubbles;
+ bool isSingleIssue;
+ bool breaksGroup;
+ CycleCount_t numBubbles;
// Feasible slots to use for instructions in this class.
// The size of vector S[] is `numSlots'.
struct {
resourceId_t resourceId;
unsigned startCycle;
- int numCycles;
+ int numCycles;
} V[MAX_NUM_CYCLES];
};
struct InstrRUsageDelta {
MachineOpCode opCode;
- resourceId_t resourceId;
+ resourceId_t resourceId;
unsigned startCycle;
- int numCycles;
+ int numCycles;
};
// Specify instruction issue restrictions for individual instructions
// that differ from the common rules for the class.
//
struct InstrIssueDelta {
- MachineOpCode opCode;
- bool isSingleIssue;
- bool breaksGroup;
- CycleCount_t numBubbles;
+ MachineOpCode opCode;
+ bool isSingleIssue;
+ bool breaksGroup;
+ CycleCount_t numBubbles;
};
struct InstrRUsage {
- bool sameAsClass;
+ bool sameAsClass;
// Issue restrictions for this instruction
- bool isSingleIssue;
- bool breaksGroup;
- CycleCount_t numBubbles;
+ bool isSingleIssue;
+ bool breaksGroup;
+ CycleCount_t numBubbles;
// Feasible slots to use for this instruction.
std::vector<bool> feasibleSlots;
// Resource usages for this instruction, with one resource vector per cycle.
- CycleCount_t numCycles;
+ CycleCount_t numCycles;
std::vector<std::vector<resourceId_t> > resourcesByCycle;
private:
numBubbles = delta.numBubbles;
}
- void addUsageDelta (const InstrRUsageDelta& delta);
- void setMaxSlots (int maxNumSlots) {
+ void addUsageDelta(const InstrRUsageDelta& delta);
+ void setMaxSlots(int maxNumSlots) {
feasibleSlots.resize(maxNumSlots);
}
- friend class TargetSchedInfo; // give access to these functions
+ friend class TargetSchedInfo; // give access to these functions
};
const TargetMachine& target;
unsigned maxNumIssueTotal;
- int longestIssueConflict;
+ int longestIssueConflict;
protected:
inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
TargetSchedInfo(const TargetSchedInfo &); // DO NOT IMPLEMENT
void operator=(const TargetSchedInfo &); // DO NOT IMPLEMENT
public:
- /*ctor*/ TargetSchedInfo (const TargetMachine& tgt,
- int _numSchedClasses,
- const InstrClassRUsage* _classRUsages,
- const InstrRUsageDelta* _usageDeltas,
- const InstrIssueDelta* _issueDeltas,
- unsigned _numUsageDeltas,
- unsigned _numIssueDeltas);
- /*dtor*/ virtual ~TargetSchedInfo() {}
+ TargetSchedInfo(const TargetMachine& tgt,
+ int _numSchedClasses,
+ const InstrClassRUsage* _classRUsages,
+ const InstrRUsageDelta* _usageDeltas,
+ const InstrIssueDelta* _issueDeltas,
+ unsigned _numUsageDeltas,
+ unsigned _numIssueDeltas);
+ virtual ~TargetSchedInfo() {}
inline const TargetInstrInfo& getInstrInfo() const {
return *mii;
}
- inline int getNumSchedClasses() const {
+ inline int getNumSchedClasses() const {
return numSchedClasses;
}
return classRUsages[sc].maxNumIssue;
}
- inline InstrSchedClass getSchedClass (MachineOpCode opCode) const {
+ inline InstrSchedClass getSchedClass(MachineOpCode opCode) const {
return getInstrInfo().getSchedClass(opCode);
}
- inline bool instrCanUseSlot (MachineOpCode opCode,
- unsigned s) const {
+ inline bool instrCanUseSlot(MachineOpCode opCode,
+ unsigned s) const {
assert(s < getInstrRUsage(opCode).feasibleSlots.size() && "Invalid slot!");
return getInstrRUsage(opCode).feasibleSlots[s];
}
- inline int getLongestIssueConflict () const {
+ inline int getLongestIssueConflict() const {
return longestIssueConflict;
}
- inline int getMinIssueGap (MachineOpCode fromOp,
- MachineOpCode toOp) const {
+ inline int getMinIssueGap(MachineOpCode fromOp,
+ MachineOpCode toOp) const {
assert(fromOp < (int) issueGaps.size());
const std::vector<int>& toGaps = issueGaps[fromOp];
return (toOp < (int) toGaps.size())? toGaps[toOp] : 0;
}
inline const std::vector<MachineOpCode>&
- getConflictList(MachineOpCode opCode) const {
+ getConflictList(MachineOpCode opCode) const {
assert(opCode < (int) conflictLists.size());
return conflictLists[opCode];
}
- inline bool isSingleIssue (MachineOpCode opCode) const {
+ inline bool isSingleIssue(MachineOpCode opCode) const {
return getInstrRUsage(opCode).isSingleIssue;
}
- inline bool breaksIssueGroup (MachineOpCode opCode) const {
+ inline bool breaksIssueGroup(MachineOpCode opCode) const {
return getInstrRUsage(opCode).breaksGroup;
}
- inline unsigned numBubblesAfter (MachineOpCode opCode) const {
+ inline unsigned numBubblesAfter(MachineOpCode opCode) const {
return getInstrRUsage(opCode).numBubbles;
}
protected:
- virtual void initializeResources ();
+ virtual void initializeResources();
private:
void computeInstrResources(const std::vector<InstrRUsage>& instrRUForClasses);
std::vector<std::pair<int,int> > resourceNumVector;
protected:
- unsigned numSchedClasses;
+ unsigned numSchedClasses;
const TargetInstrInfo* mii;
- const InstrClassRUsage* classRUsages; // raw array by sclass
- const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
- const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
- unsigned numUsageDeltas;
- unsigned numIssueDeltas;
+ const InstrClassRUsage* classRUsages; // raw array by sclass
+ const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
+ const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
+ unsigned numUsageDeltas;
+ unsigned numIssueDeltas;
std::vector<InstrRUsage> instrRUsages; // indexed by opcode
std::vector<std::vector<int> > issueGaps; // indexed by [opcode1][opcode2]
std::vector<std::vector<MachineOpCode> >
- conflictLists; // indexed by [opcode]
+ conflictLists; // indexed by [opcode]
friend class ModuloSchedulingPass;
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