[AArch64] Handle extract_subvector(..., 0) in ISel.

[AArch64] Handle extract_subvector(..., 0) in ISel.

Summary:
Lowering this pattern early to an `EXTRACT_SUBREG` was making it impossible to match larger patterns in tblgen that use `extract_subvector(..., 0)` as part of the their input pattern.

It seems like there will exist somewhere a better way of specifying this pattern over all relevant register value types, but I didn't manage to find it.

Reviewers: t.p.northover, jmolloy

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D14207

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252464 91177308-0d34-0410-b5e6-96231b3b80d8