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[AArch64] Teach DAGCombiner that converting two consecutive loads into a vector load...
authorJames Molloy <james.molloy@arm.com>
Sat, 2 Aug 2014 14:51:24 +0000 (14:51 +0000)
committerJames Molloy <james.molloy@arm.com>
Sat, 2 Aug 2014 14:51:24 +0000 (14:51 +0000)
commite411c38de930eff5dbe9cfe2833af2322917e872
tree47c7d433017af65768a1cea66c6ca66f4c5f1412tree | snapshot
parentcaf471e8202bb32ca16b5d176de533b3aa53323ecommit | diff
[AArch64] Teach DAGCombiner that converting two consecutive loads into a vector load is not a good transform when paired loads are available.

The combiner was creating Q-register loads and stores, which then had to be spilled because there are no callee-save Q registers!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214634 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff | blob | history
test/CodeGen/AArch64/paired-load.ll [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors