emit an enum value for the # of target registers.

[oota-llvm.git] / utils / TableGen / RegisterInfoEmitter.cpp

diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index 1799ac49e3c58e151a939272b11a9a8ce5e5fb14..ac26837830eb1a3b2e72480434f7eb6949d144d6 100644 (file)
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -19,6 +19,7 @@
 #include "Record.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/Support/Streams.h"
 #include <set>
 using namespace llvm;
 
@@ -37,8 +38,8 @@ void RegisterInfoEmitter::runEnums(std::ostream &OS) {
   OS << "  enum {\n    NoRegister,\n";
 
   for (unsigned i = 0, e = Registers.size(); i != e; ++i)
-    OS << "    " << Registers[i].getName() << (i != (e-1) ? ", \t// " : "  \t// ") << i+1 << "\n";
-
+    OS << "    " << Registers[i].getName() << ", \t// " << i+1 << "\n";
+  OS << "    NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
   OS << "  };\n";
   if (!Namespace.empty())
     OS << "}\n";
@@ -68,6 +69,15 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) {
   if (!RegisterClasses.empty()) {
     OS << "namespace " << RegisterClasses[0].Namespace
        << " { // Register classes\n";
+       
+    OS << "  enum {\n";
+    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
+      if (i) OS << ",\n";
+      OS << "    " << RegisterClasses[i].getName() << "RegClassID";
+      if (!i) OS << " = 1";
+    }
+    OS << "\n  };\n\n";
+
     for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
       const std::string &Name = RegisterClasses[i].getName();
 
@@ -127,7 +137,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
     std::string Name = RC.TheDef->getName();
   
     // Emit the register list now.
-    OS << "  // " << Name << " Register Class...\n  const unsigned " << Name
+    OS << "  // " << Name << " Register Class...\n"
+       << "  static const unsigned " << Name
        << "[] = {\n    ";
     for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
       Record *Reg = RC.Elements[i];
@@ -148,8 +159,9 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
     
     // Emit the register list now.
     OS << "  // " << Name 
-      << " Register Class Value Types...\n  const MVT::ValueType " << Name
-      << "[] = {\n    ";
+       << " Register Class Value Types...\n"
+       << "  static const MVT::ValueType " << Name
+       << "[] = {\n    ";
     for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
       OS << RC.VTs[i] << ", ";
     OS << "MVT::Other\n  };\n\n";
@@ -163,7 +175,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
     for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
       OS << "  " << RegisterClasses[i].getName()  << "Class\t"
          << RegisterClasses[i].getName() << "RegClass;\n";
-
+         
     std::map<unsigned, std::set<unsigned> > SuperClassMap;
     OS << "\n";
     // Emit the sub-classes array for each RegisterClass
@@ -180,7 +192,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
       }
 
       OS << "  // " << Name 
-         << " Register Class sub-classes...\n  const TargetRegisterClass* "
+         << " Register Class sub-classes...\n"
+         << "  static const TargetRegisterClass* const "
          << Name << "Subclasses [] = {\n    ";
 
       bool Empty = true;
@@ -214,7 +227,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
       std::string Name = RC.TheDef->getName();
 
       OS << "  // " << Name 
-         << " Register Class super-classes...\n  const TargetRegisterClass* "
+         << " Register Class super-classes...\n"
+         << "  static const TargetRegisterClass* const "
          << Name << "Superclasses [] = {\n    ";
 
       bool Empty = true;
@@ -240,6 +254,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
       OS << RC.MethodBodies << "\n";
       OS << RC.getName() << "Class::" << RC.getName() 
          << "Class()  : TargetRegisterClass("
+         << RC.getName() + "RegClassID" << ", "
          << RC.getName() + "VTs" << ", "
          << RC.getName() + "Subclasses" << ", "
          << RC.getName() + "Superclasses" << ", "
@@ -270,15 +285,15 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
     for (unsigned j = 0, e = LI.size(); j != e; ++j) {
       Record *Reg = LI[j];
       if (RegisterAliases[R].count(Reg))
-        std::cerr << "Warning: register alias between " << getQualifiedName(R)
-                  << " and " << getQualifiedName(Reg)
-                  << " specified multiple times!\n";
+        cerr << "Warning: register alias between " << getQualifiedName(R)
+             << " and " << getQualifiedName(Reg)
+             << " specified multiple times!\n";
       RegisterAliases[R].insert(Reg);
 
       if (RegisterAliases[Reg].count(R))
-        std::cerr << "Warning: register alias between " << getQualifiedName(R)
-                  << " and " << getQualifiedName(Reg)
-                  << " specified multiple times!\n";
+        cerr << "Warning: register alias between " << getQualifiedName(R)
+             << " and " << getQualifiedName(Reg)
+             << " specified multiple times!\n";
       RegisterAliases[Reg].insert(R);
     }
   }