//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "pseudo-lowering"
#include "CodeGenInstruction.h"
-#include "PseudoLoweringEmitter.h"
-#include "llvm/TableGen/Error.h"
-#include "llvm/TableGen/Record.h"
+#include "CodeGenTarget.h"
#include "llvm/ADT/IndexedMap.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringMap.h"
-#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/TableGen/Error.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
#include <vector>
using namespace llvm;
+#define DEBUG_TYPE "pseudo-lowering"
+
+namespace {
+class PseudoLoweringEmitter {
+ struct OpData {
+ enum MapKind { Operand, Imm, Reg };
+ MapKind Kind;
+ union {
+ unsigned Operand; // Operand number mapped to.
+ uint64_t Imm; // Integer immedate value.
+ Record *Reg; // Physical register.
+ } Data;
+ };
+ struct PseudoExpansion {
+ CodeGenInstruction Source; // The source pseudo instruction definition.
+ CodeGenInstruction Dest; // The destination instruction to lower to.
+ IndexedMap<OpData> OperandMap;
+
+ PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d,
+ IndexedMap<OpData> &m) :
+ Source(s), Dest(d), OperandMap(m) {}
+ };
+
+ RecordKeeper &Records;
+
+ // It's overkill to have an instance of the full CodeGenTarget object,
+ // but it loads everything on demand, not in the constructor, so it's
+ // lightweight in performance, so it works out OK.
+ CodeGenTarget Target;
+
+ SmallVector<PseudoExpansion, 64> Expansions;
+
+ unsigned addDagOperandMapping(Record *Rec, DagInit *Dag,
+ CodeGenInstruction &Insn,
+ IndexedMap<OpData> &OperandMap,
+ unsigned BaseIdx);
+ void evaluateExpansion(Record *Pseudo);
+ void emitLoweringEmitter(raw_ostream &o);
+public:
+ PseudoLoweringEmitter(RecordKeeper &R) : Records(R), Target(R) {}
+
+ /// run - Output the pseudo-lowerings.
+ void run(raw_ostream &o);
+};
+} // End anonymous namespace
+
// FIXME: This pass currently can only expand a pseudo to a single instruction.
// The pseudo expansion really should take a list of dags, not just
// a single dag, so we can do fancier things.
IndexedMap<OpData> &OperandMap, unsigned BaseIdx) {
unsigned OpsAdded = 0;
for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
- if (DefInit *DI = dynamic_cast<DefInit*>(Dag->getArg(i))) {
+ if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) {
// Physical register reference. Explicit check for the special case
// "zero_reg" definition.
if (DI->getDef()->isSubClassOf("Register") ||
// FIXME: We probably shouldn't ever get a non-zero BaseIdx here.
assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!");
if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
- throw TGError(Rec->getLoc(),
+ PrintFatalError(Rec->getLoc(),
"Pseudo operand type '" + DI->getDef()->getName() +
"' does not match expansion operand type '" +
Insn.Operands[BaseIdx + i].Rec->getName() + "'");
for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
OpsAdded += Insn.Operands[i].MINumOperands;
- } else if (IntInit *II = dynamic_cast<IntInit*>(Dag->getArg(i))) {
+ } else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) {
OperandMap[BaseIdx + i].Kind = OpData::Imm;
OperandMap[BaseIdx + i].Data.Imm = II->getValue();
++OpsAdded;
- } else if (DagInit *SubDag = dynamic_cast<DagInit*>(Dag->getArg(i))) {
+ } else if (DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) {
// Just add the operands recursively. This is almost certainly
// a constant value for a complex operand (> 1 MI operand).
unsigned NewOps =
assert(Dag && "Missing result instruction in pseudo expansion!");
DEBUG(dbgs() << " Result: " << *Dag << "\n");
- DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
+ DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator());
if (!OpDef)
- throw TGError(Rec->getLoc(), Rec->getName() +
+ PrintFatalError(Rec->getLoc(), Rec->getName() +
" has unexpected operator type!");
Record *Operator = OpDef->getDef();
if (!Operator->isSubClassOf("Instruction"))
- throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
- "' is not an instruction!");
+ PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
+ "' is not an instruction!");
CodeGenInstruction Insn(Operator);
if (Insn.isCodeGenOnly || Insn.isPseudo)
- throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
- "' cannot be another pseudo instruction!");
+ PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
+ "' cannot be another pseudo instruction!");
if (Insn.Operands.size() != Dag->getNumArgs())
- throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
- "' operand count mismatch");
+ PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
+ "' operand count mismatch");
unsigned NumMIOperands = 0;
for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
// If there are more operands that weren't in the DAG, they have to
// be operands that have default values, or we have an error. Currently,
- // PredicateOperand and OptionalDefOperand both have default values.
-
+ // Operands that are a subclass of OperandWithDefaultOp have default values.
// Validate that each result pattern argument has a matching (by name)
// argument in the source instruction, in either the (outs) or (ins) list.
StringMap<unsigned>::iterator SourceOp =
SourceOperands.find(Dag->getArgName(i));
if (SourceOp == SourceOperands.end())
- throw TGError(Rec->getLoc(),
- "Pseudo output operand '" + Dag->getArgName(i) +
- "' has no matching source operand.");
+ PrintFatalError(Rec->getLoc(),
+ "Pseudo output operand '" + Dag->getArgName(i) +
+ "' has no matching source operand.");
// Map the source operand to the destination operand index for each
// MachineInstr operand.
for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
// Emit file header.
- EmitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o);
+ emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o);
o << "bool " << Target.getName() + "AsmPrinter" << "::\n"
<< "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n"
- << " const MachineInstr *MI) {\n"
- << " switch (MI->getOpcode()) {\n"
- << " default: return false;\n";
- for (unsigned i = 0, e = Expansions.size(); i != e; ++i) {
- PseudoExpansion &Expansion = Expansions[i];
- CodeGenInstruction &Source = Expansion.Source;
- CodeGenInstruction &Dest = Expansion.Dest;
- o << " case " << Source.Namespace << "::"
- << Source.TheDef->getName() << ": {\n"
- << " MCInst TmpInst;\n"
- << " MCOperand MCOp;\n"
- << " TmpInst.setOpcode(" << Dest.Namespace << "::"
- << Dest.TheDef->getName() << ");\n";
-
- // Copy the operands from the source instruction.
- // FIXME: Instruction operands with defaults values (predicates and cc_out
- // in ARM, for example shouldn't need explicit values in the
- // expansion DAG.
- unsigned MIOpNo = 0;
- for (unsigned OpNo = 0, E = Dest.Operands.size(); OpNo != E;
- ++OpNo) {
- o << " // Operand: " << Dest.Operands[OpNo].Name << "\n";
- for (unsigned i = 0, e = Dest.Operands[OpNo].MINumOperands;
- i != e; ++i) {
- switch (Expansion.OperandMap[MIOpNo + i].Kind) {
- case OpData::Operand:
- o << " lowerOperand(MI->getOperand("
- << Source.Operands[Expansion.OperandMap[MIOpNo].Data
- .Operand].MIOperandNo + i
- << "), MCOp);\n"
- << " TmpInst.addOperand(MCOp);\n";
- break;
- case OpData::Imm:
- o << " TmpInst.addOperand(MCOperand::CreateImm("
- << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
- break;
- case OpData::Reg: {
- Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
- o << " TmpInst.addOperand(MCOperand::CreateReg(";
- // "zero_reg" is special.
- if (Reg->getName() == "zero_reg")
- o << "0";
- else
- o << Reg->getValueAsString("Namespace") << "::" << Reg->getName();
- o << "));\n";
- break;
- }
+ << " const MachineInstr *MI) {\n";
+
+ if (!Expansions.empty()) {
+ o << " switch (MI->getOpcode()) {\n"
+ << " default: return false;\n";
+ for (auto &Expansion : Expansions) {
+ CodeGenInstruction &Source = Expansion.Source;
+ CodeGenInstruction &Dest = Expansion.Dest;
+ o << " case " << Source.Namespace << "::"
+ << Source.TheDef->getName() << ": {\n"
+ << " MCInst TmpInst;\n"
+ << " MCOperand MCOp;\n"
+ << " TmpInst.setOpcode(" << Dest.Namespace << "::"
+ << Dest.TheDef->getName() << ");\n";
+
+ // Copy the operands from the source instruction.
+ // FIXME: Instruction operands with defaults values (predicates and cc_out
+ // in ARM, for example shouldn't need explicit values in the
+ // expansion DAG.
+ unsigned MIOpNo = 0;
+ for (const auto &DestOperand : Dest.Operands) {
+ o << " // Operand: " << DestOperand.Name << "\n";
+ for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) {
+ switch (Expansion.OperandMap[MIOpNo + i].Kind) {
+ case OpData::Operand:
+ o << " lowerOperand(MI->getOperand("
+ << Source.Operands[Expansion.OperandMap[MIOpNo].Data
+ .Operand].MIOperandNo + i
+ << "), MCOp);\n"
+ << " TmpInst.addOperand(MCOp);\n";
+ break;
+ case OpData::Imm:
+ o << " TmpInst.addOperand(MCOperand::createImm("
+ << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
+ break;
+ case OpData::Reg: {
+ Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
+ o << " TmpInst.addOperand(MCOperand::createReg(";
+ // "zero_reg" is special.
+ if (Reg->getName() == "zero_reg")
+ o << "0";
+ else
+ o << Reg->getValueAsString("Namespace") << "::"
+ << Reg->getName();
+ o << "));\n";
+ break;
+ }
+ }
}
+ MIOpNo += DestOperand.MINumOperands;
}
- MIOpNo += Dest.Operands[OpNo].MINumOperands;
- }
- if (Dest.Operands.isVariadic) {
- o << " // variable_ops\n";
- o << " for (unsigned i = " << MIOpNo
- << ", e = MI->getNumOperands(); i != e; ++i)\n"
- << " if (lowerOperand(MI->getOperand(i), MCOp))\n"
- << " TmpInst.addOperand(MCOp);\n";
+ if (Dest.Operands.isVariadic) {
+ MIOpNo = Source.Operands.size() + 1;
+ o << " // variable_ops\n";
+ o << " for (unsigned i = " << MIOpNo
+ << ", e = MI->getNumOperands(); i != e; ++i)\n"
+ << " if (lowerOperand(MI->getOperand(i), MCOp))\n"
+ << " TmpInst.addOperand(MCOp);\n";
+ }
+ o << " EmitToStreamer(OutStreamer, TmpInst);\n"
+ << " break;\n"
+ << " }\n";
}
- o << " OutStreamer.EmitInstruction(TmpInst);\n"
- << " break;\n"
- << " }\n";
- }
- o << " }\n return true;\n}\n\n";
+ o << " }\n return true;";
+ } else
+ o << " return false;";
+
+ o << "\n}\n\n";
}
void PseudoLoweringEmitter::run(raw_ostream &o) {
Record *ExpansionClass = Records.getClass("PseudoInstExpansion");
- Record *InstructionClass = Records.getClass("PseudoInstExpansion");
+ Record *InstructionClass = Records.getClass("Instruction");
assert(ExpansionClass && "PseudoInstExpansion class definition missing!");
assert(InstructionClass && "Instruction class definition missing!");
std::vector<Record*> Insts;
- for (std::map<std::string, Record*>::const_iterator I =
- Records.getDefs().begin(), E = Records.getDefs().end(); I != E; ++I) {
- if (I->second->isSubClassOf(ExpansionClass) &&
- I->second->isSubClassOf(InstructionClass))
- Insts.push_back(I->second);
+ for (const auto &D : Records.getDefs()) {
+ if (D.second->isSubClassOf(ExpansionClass) &&
+ D.second->isSubClassOf(InstructionClass))
+ Insts.push_back(D.second.get());
}
// Process the pseudo expansion definitions, validating them as we do so.
emitLoweringEmitter(o);
}
+namespace llvm {
+
+void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS) {
+ PseudoLoweringEmitter(RK).run(OS);
+}
+
+} // End llvm namespace
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