//
//===----------------------------------------------------------------------===//
//
-// This tablegen backend emits a "fast" instruction selector.
+// This tablegen backend emits code for use by the "fast" instruction
+// selection algorithm. See the comments at the top of
+// lib/CodeGen/SelectionDAG/FastISel.cpp for background.
//
-// This instruction selection method is designed to emit very poor code
-// quickly. Also, it is not designed to do much lowering, so most illegal
-// types (e.g. i64 on 32-bit targets) and operations (e.g. calls) are not
-// supported and cannot easily be added. Blocks containing operations
-// that are not supported need to be handled by a more capable selector,
-// such as the SelectionDAG selector.
+// This file scans through the target's tablegen instruction-info files
+// and extracts instructions with obvious-looking patterns, and it emits
+// code to look up these instructions by type and operator.
//
-// The intended use for "fast" instruction selection is "-O0" mode
-// compilation, where the quality of the generated code is irrelevant when
-// weighed against the speed at which the code can be generated.
-//
-// If compile time is so important, you might wonder why we don't just
-// skip codegen all-together, emit LLVM bytecode files, and execute them
-// with an interpreter. The answer is that it would complicate linking and
-// debugging, and also because that isn't how a compiler is expected to
-// work in some circles.
-//
-// If you need better generated code or more lowering than what this
-// instruction selector provides, use the SelectionDAG (DAGISel) instruction
-// selector instead. If you're looking here because SelectionDAG isn't fast
-// enough, consider looking into improving the SelectionDAG infastructure
-// instead. At the time of this writing there remain several major
-// opportunities for improvement.
-//
//===----------------------------------------------------------------------===//
#include "FastISelEmitter.h"
#include "Record.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Support/Streams.h"
+#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/VectorExtras.h"
using namespace llvm;
namespace {
+/// InstructionMemo - This class holds additional information about an
+/// instruction needed to emit code for it.
+///
+struct InstructionMemo {
+ std::string Name;
+ const CodeGenRegisterClass *RC;
+ std::string SubRegNo;
+ std::vector<std::string>* PhysRegs;
+};
+
/// OperandsSignature - This class holds a description of a list of operand
/// types. It has utility methods for emitting text based on the operands.
///
bool initialize(TreePatternNode *InstPatNode,
const CodeGenTarget &Target,
MVT::SimpleValueType VT) {
- if (!InstPatNode->isLeaf() &&
- InstPatNode->getOperator()->getName() == "imm") {
- Operands.push_back("i");
- return true;
- }
- if (!InstPatNode->isLeaf() &&
- InstPatNode->getOperator()->getName() == "fpimm") {
- Operands.push_back("f");
- return true;
+
+ if (!InstPatNode->isLeaf()) {
+ if (InstPatNode->getOperator()->getName() == "imm") {
+ Operands.push_back("i");
+ return true;
+ }
+ if (InstPatNode->getOperator()->getName() == "fpimm") {
+ Operands.push_back("f");
+ return true;
+ }
}
-
+
const CodeGenRegisterClass *DstRC = 0;
-
+
for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
TreePatternNode *Op = InstPatNode->getChild(i);
+
// For now, filter out any operand with a predicate.
- if (!Op->getPredicateFn().empty())
- return false;
// For now, filter out any operand with multiple values.
- if (Op->getExtTypes().size() != 1)
+ if (!Op->getPredicateFns().empty() ||
+ Op->getNumTypes() != 1)
return false;
+
+ assert(Op->hasTypeSet(0) && "Type infererence not done?");
// For now, all the operands must have the same type.
- if (Op->getTypeNum(0) != VT)
+ if (Op->getType(0) != VT)
return false;
+
if (!Op->isLeaf()) {
if (Op->getOperator()->getName() == "imm") {
Operands.push_back("i");
- return true;
+ continue;
}
if (Op->getOperator()->getName() == "fpimm") {
Operands.push_back("f");
- return true;
+ continue;
}
// For now, ignore other non-leaf nodes.
return false;
if (!OpDI)
return false;
Record *OpLeafRec = OpDI->getDef();
- // TODO: handle instructions which have physreg operands.
- if (OpLeafRec->isSubClassOf("Register"))
- return false;
// For now, the only other thing we accept is register operands.
- if (!OpLeafRec->isSubClassOf("RegisterClass"))
+
+ const CodeGenRegisterClass *RC = 0;
+ if (OpLeafRec->isSubClassOf("RegisterClass"))
+ RC = &Target.getRegisterClass(OpLeafRec);
+ else if (OpLeafRec->isSubClassOf("Register"))
+ RC = Target.getRegisterClassForRegister(OpLeafRec);
+ else
return false;
- // For now, require the register operands' register classes to all
- // be the same.
- const CodeGenRegisterClass *RC = &Target.getRegisterClass(OpLeafRec);
+
+ // For now, this needs to be a register class of some sort.
if (!RC)
return false;
- // For now, all the operands must have the same register class.
+
+ // For now, all the operands must have the same register class or be
+ // a strict subclass of the destination.
if (DstRC) {
- if (DstRC != RC)
+ if (DstRC != RC && !DstRC->hasSubClass(RC))
return false;
} else
DstRC = RC;
return true;
}
- void PrintParameters(std::ostream &OS) const {
+ void PrintParameters(raw_ostream &OS) const {
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
if (Operands[i] == "r") {
- OS << "unsigned Op" << i;
+ OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
} else if (Operands[i] == "i") {
OS << "uint64_t imm" << i;
} else if (Operands[i] == "f") {
}
}
- void PrintArguments(std::ostream &OS) const {
+ void PrintArguments(raw_ostream &OS,
+ const std::vector<std::string>& PR) const {
+ assert(PR.size() == Operands.size());
+ bool PrintedArg = false;
+ for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+ if (PR[i] != "")
+ // Implicit physical register operand.
+ continue;
+
+ if (PrintedArg)
+ OS << ", ";
+ if (Operands[i] == "r") {
+ OS << "Op" << i << ", Op" << i << "IsKill";
+ PrintedArg = true;
+ } else if (Operands[i] == "i") {
+ OS << "imm" << i;
+ PrintedArg = true;
+ } else if (Operands[i] == "f") {
+ OS << "f" << i;
+ PrintedArg = true;
+ } else {
+ assert("Unknown operand kind!");
+ abort();
+ }
+ }
+ }
+
+ void PrintArguments(raw_ostream &OS) const {
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
if (Operands[i] == "r") {
- OS << "Op" << i;
+ OS << "Op" << i << ", Op" << i << "IsKill";
} else if (Operands[i] == "i") {
OS << "imm" << i;
} else if (Operands[i] == "f") {
}
}
- void PrintManglingSuffix(std::ostream &OS) const {
+
+ void PrintManglingSuffix(raw_ostream &OS,
+ const std::vector<std::string>& PR) const {
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+ if (PR[i] != "")
+ // Implicit physical register operand. e.g. Instruction::Mul expect to
+ // select to a binary op. On x86, mul may take a single operand with
+ // the other operand being implicit. We must emit something that looks
+ // like a binary instruction except for the very inner FastEmitInst_*
+ // call.
+ continue;
OS << Operands[i];
}
}
-};
-/// InstructionMemo - This class holds additional information about an
-/// instruction needed to emit code for it.
-///
-struct InstructionMemo {
- std::string Name;
- const CodeGenRegisterClass *RC;
+ void PrintManglingSuffix(raw_ostream &OS) const {
+ for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+ OS << Operands[i];
+ }
+ }
};
class FastISelMap {
typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
- typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> OperandsOpcodeTypeRetPredMap;
+ typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
+ OperandsOpcodeTypeRetPredMap;
OperandsOpcodeTypeRetPredMap SimplePatterns;
explicit FastISelMap(std::string InstNS);
void CollectPatterns(CodeGenDAGPatterns &CGP);
- void PrintClass(std::ostream &OS);
- void PrintFunctionDefinitions(std::ostream &OS);
+ void PrintFunctionDefinitions(raw_ostream &OS);
};
}
Record *Op = Dst->getOperator();
if (!Op->isSubClassOf("Instruction"))
continue;
- CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op->getName());
- if (II.OperandList.empty())
+ CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
+ if (II.Operands.size() == 0)
+ continue;
+
+ // For now, ignore multi-instruction patterns.
+ bool MultiInsts = false;
+ for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
+ TreePatternNode *ChildOp = Dst->getChild(i);
+ if (ChildOp->isLeaf())
+ continue;
+ if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
+ MultiInsts = true;
+ break;
+ }
+ }
+ if (MultiInsts)
continue;
// For now, ignore instructions where the first operand is not an
// output register.
- Record *Op0Rec = II.OperandList[0].Rec;
- if (!Op0Rec->isSubClassOf("RegisterClass"))
- continue;
- const CodeGenRegisterClass *DstRC = &Target.getRegisterClass(Op0Rec);
- if (!DstRC)
- continue;
+ const CodeGenRegisterClass *DstRC = 0;
+ std::string SubRegNo;
+ if (Op->getName() != "EXTRACT_SUBREG") {
+ Record *Op0Rec = II.Operands[0].Rec;
+ if (!Op0Rec->isSubClassOf("RegisterClass"))
+ continue;
+ DstRC = &Target.getRegisterClass(Op0Rec);
+ if (!DstRC)
+ continue;
+ } else {
+ // If this isn't a leaf, then continue since the register classes are
+ // a bit too complicated for now.
+ if (!Dst->getChild(1)->isLeaf()) continue;
+
+ DefInit *SR = dynamic_cast<DefInit*>(Dst->getChild(1)->getLeafValue());
+ if (SR)
+ SubRegNo = getQualifiedName(SR->getDef());
+ else
+ SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString();
+ }
// Inspect the pattern.
TreePatternNode *InstPatNode = Pattern.getSrcPattern();
if (!InstPatNode) continue;
if (InstPatNode->isLeaf()) continue;
+ // Ignore multiple result nodes for now.
+ if (InstPatNode->getNumTypes() > 1) continue;
+
Record *InstPatOp = InstPatNode->getOperator();
std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
- MVT::SimpleValueType RetVT = InstPatNode->getTypeNum(0);
+ MVT::SimpleValueType RetVT = MVT::isVoid;
+ if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0);
MVT::SimpleValueType VT = RetVT;
- if (InstPatNode->getNumChildren())
- VT = InstPatNode->getChild(0)->getTypeNum(0);
+ if (InstPatNode->getNumChildren()) {
+ assert(InstPatNode->getChild(0)->getNumTypes() == 1);
+ VT = InstPatNode->getChild(0)->getType(0);
+ }
// For now, filter out instructions which just set a register to
// an Operand or an immediate, like MOV32ri.
continue;
// For now, filter out any instructions with predicates.
- if (!InstPatNode->getPredicateFn().empty())
+ if (!InstPatNode->getPredicateFns().empty())
continue;
// Check all the operands.
if (!Operands.initialize(InstPatNode, Target, VT))
continue;
+ std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
+ if (!InstPatNode->isLeaf() &&
+ (InstPatNode->getOperator()->getName() == "imm" ||
+ InstPatNode->getOperator()->getName() == "fpimmm"))
+ PhysRegInputs->push_back("");
+ else if (!InstPatNode->isLeaf()) {
+ for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
+ TreePatternNode *Op = InstPatNode->getChild(i);
+ if (!Op->isLeaf()) {
+ PhysRegInputs->push_back("");
+ continue;
+ }
+
+ DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
+ Record *OpLeafRec = OpDI->getDef();
+ std::string PhysReg;
+ if (OpLeafRec->isSubClassOf("Register")) {
+ PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \
+ "Namespace")->getValue())->getValue();
+ PhysReg += "::";
+
+ std::vector<CodeGenRegister> Regs = Target.getRegisters();
+ for (unsigned i = 0; i < Regs.size(); ++i) {
+ if (Regs[i].TheDef == OpLeafRec) {
+ PhysReg += Regs[i].getName();
+ break;
+ }
+ }
+ }
+
+ PhysRegInputs->push_back(PhysReg);
+ }
+ } else
+ PhysRegInputs->push_back("");
+
// Get the predicate that guards this pattern.
std::string PredicateCheck = Pattern.getPredicateCheck();
// Ok, we found a pattern that we can handle. Remember it.
InstructionMemo Memo = {
Pattern.getDstPattern()->getOperator()->getName(),
- DstRC
+ DstRC,
+ SubRegNo,
+ PhysRegInputs
};
- assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
- "Duplicate pattern!");
- SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
- }
-}
-
-void FastISelMap::PrintClass(std::ostream &OS) {
- // Declare the target FastISel class.
- OS << "class FastISel : public llvm::FastISel {\n";
- for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
- OE = SimplePatterns.end(); OI != OE; ++OI) {
- const OperandsSignature &Operands = OI->first;
- const OpcodeTypeRetPredMap &OTM = OI->second;
-
- for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
- I != E; ++I) {
- const std::string &Opcode = I->first;
- const TypeRetPredMap &TM = I->second;
-
- for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
- TI != TE; ++TI) {
- MVT::SimpleValueType VT = TI->first;
- const RetPredMap &RM = TI->second;
-
- if (RM.size() != 1)
- for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
- RI != RE; ++RI) {
- MVT::SimpleValueType RetVT = RI->first;
- OS << " unsigned FastEmit_" << getLegalCName(Opcode)
- << "_" << getLegalCName(getName(VT)) << "_"
- << getLegalCName(getName(RetVT)) << "_";
- Operands.PrintManglingSuffix(OS);
- OS << "(";
- Operands.PrintParameters(OS);
- OS << ");\n";
- }
-
- OS << " unsigned FastEmit_" << getLegalCName(Opcode)
- << "_" << getLegalCName(getName(VT)) << "_";
- Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType RetVT";
- if (!Operands.empty())
- OS << ", ";
- Operands.PrintParameters(OS);
- OS << ");\n";
- }
+ if (SimplePatterns[Operands][OpcodeName][VT][RetVT]
+ .count(PredicateCheck))
+ throw TGError(Pattern.getSrcRecord()->getLoc(), "Duplicate record!");
- OS << " unsigned FastEmit_" << getLegalCName(Opcode) << "_";
- Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT";
- if (!Operands.empty())
- OS << ", ";
- Operands.PrintParameters(OS);
- OS << ");\n";
- }
-
- OS << " unsigned FastEmit_";
- Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode";
- if (!Operands.empty())
- OS << ", ";
- Operands.PrintParameters(OS);
- OS << ");\n";
+ SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
}
- OS << "\n";
-
- // Declare the Subtarget member, which is used for predicate checks.
- OS << " const " << InstNS.substr(0, InstNS.size() - 2)
- << "Subtarget *Subtarget;\n";
- OS << "\n";
-
- // Declare the constructor.
- OS << "public:\n";
- OS << " explicit FastISel(MachineFunction &mf)\n";
- OS << " : llvm::FastISel(mf),\n";
- OS << " Subtarget(&TM.getSubtarget<" << InstNS.substr(0, InstNS.size() - 2)
- << "Subtarget>()) {}\n";
- OS << "};\n";
- OS << "\n";
}
-void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
+void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) {
// Now emit code for all the patterns that we collected.
for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
OE = SimplePatterns.end(); OI != OE; ++OI) {
const PredMap &PM = RI->second;
bool HasPred = false;
- OS << "unsigned FastISel::FastEmit_"
+ OS << "unsigned FastEmit_"
<< getLegalCName(Opcode)
<< "_" << getLegalCName(getName(VT))
<< "_" << getLegalCName(getName(RetVT)) << "_";
PI != PE; ++PI) {
std::string PredicateCheck = PI->first;
const InstructionMemo &Memo = PI->second;
-
+
if (PredicateCheck.empty()) {
assert(!HasPred &&
"Multiple instructions match, at least one has "
"a predicate and at least one doesn't!");
} else {
- OS << " if (" + PredicateCheck + ")\n";
+ OS << " if (" + PredicateCheck + ") {\n";
OS << " ";
HasPred = true;
}
+
+ for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
+ if ((*Memo.PhysRegs)[i] != "")
+ OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
+ << "TII.get(TargetOpcode::COPY), "
+ << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
+ }
+
OS << " return FastEmitInst_";
- Operands.PrintManglingSuffix(OS);
- OS << "(" << InstNS << Memo.Name << ", ";
- OS << InstNS << Memo.RC->getName() << "RegisterClass";
- if (!Operands.empty())
- OS << ", ";
- Operands.PrintArguments(OS);
- OS << ");\n";
+ if (Memo.SubRegNo.empty()) {
+ Operands.PrintManglingSuffix(OS, *Memo.PhysRegs);
+ OS << "(" << InstNS << Memo.Name << ", ";
+ OS << InstNS << Memo.RC->getName() << "RegisterClass";
+ if (!Operands.empty())
+ OS << ", ";
+ Operands.PrintArguments(OS, *Memo.PhysRegs);
+ OS << ");\n";
+ } else {
+ OS << "extractsubreg(" << getName(RetVT);
+ OS << ", Op0, Op0IsKill, ";
+ OS << Memo.SubRegNo;
+ OS << ");\n";
+ }
+
+ if (HasPred)
+ OS << " }\n";
+
}
// Return 0 if none of the predicates were satisfied.
if (HasPred)
OS << "}\n";
OS << "\n";
}
-
+
// Emit one function for the type that demultiplexes on return type.
- OS << "unsigned FastISel::FastEmit_"
+ OS << "unsigned FastEmit_"
<< getLegalCName(Opcode) << "_"
<< getLegalCName(getName(VT)) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType RetVT";
+ OS << "(MVT RetVT";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
- OS << ") {\nswitch (RetVT) {\n";
+ OS << ") {\nswitch (RetVT.SimpleTy) {\n";
for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
RI != RE; ++RI) {
MVT::SimpleValueType RetVT = RI->first;
OS << ");\n";
}
OS << " default: return 0;\n}\n}\n\n";
-
+
} else {
// Non-variadic return type.
- OS << "unsigned FastISel::FastEmit_"
+ OS << "unsigned FastEmit_"
<< getLegalCName(Opcode) << "_"
<< getLegalCName(getName(VT)) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType RetVT";
+ OS << "(MVT RetVT";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
OS << ") {\n";
-
- OS << " if (RetVT != " << getName(RM.begin()->first)
+
+ OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first)
<< ")\n return 0;\n";
-
+
const PredMap &PM = RM.begin()->second;
bool HasPred = false;
-
+
// Emit code for each possible instruction. There may be
// multiple if there are subtarget concerns.
- for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; ++PI) {
+ for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE;
+ ++PI) {
std::string PredicateCheck = PI->first;
const InstructionMemo &Memo = PI->second;
"Multiple instructions match, at least one has "
"a predicate and at least one doesn't!");
} else {
- OS << " if (" + PredicateCheck + ")\n";
+ OS << " if (" + PredicateCheck + ") {\n";
OS << " ";
HasPred = true;
}
+
+ for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
+ if ((*Memo.PhysRegs)[i] != "")
+ OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
+ << "TII.get(TargetOpcode::COPY), "
+ << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
+ }
+
OS << " return FastEmitInst_";
- Operands.PrintManglingSuffix(OS);
- OS << "(" << InstNS << Memo.Name << ", ";
- OS << InstNS << Memo.RC->getName() << "RegisterClass";
- if (!Operands.empty())
- OS << ", ";
- Operands.PrintArguments(OS);
- OS << ");\n";
+
+ if (Memo.SubRegNo.empty()) {
+ Operands.PrintManglingSuffix(OS, *Memo.PhysRegs);
+ OS << "(" << InstNS << Memo.Name << ", ";
+ OS << InstNS << Memo.RC->getName() << "RegisterClass";
+ if (!Operands.empty())
+ OS << ", ";
+ Operands.PrintArguments(OS, *Memo.PhysRegs);
+ OS << ");\n";
+ } else {
+ OS << "extractsubreg(RetVT, Op0, Op0IsKill, ";
+ OS << Memo.SubRegNo;
+ OS << ");\n";
+ }
+
+ if (HasPred)
+ OS << " }\n";
}
-
+
// Return 0 if none of the predicates were satisfied.
if (HasPred)
OS << " return 0;\n";
}
// Emit one function for the opcode that demultiplexes based on the type.
- OS << "unsigned FastISel::FastEmit_"
+ OS << "unsigned FastEmit_"
<< getLegalCName(Opcode) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT";
+ OS << "(MVT VT, MVT RetVT";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
OS << ") {\n";
- OS << " switch (VT) {\n";
+ OS << " switch (VT.SimpleTy) {\n";
for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
TI != TE; ++TI) {
MVT::SimpleValueType VT = TI->first;
// Emit one function for the operand signature that demultiplexes based
// on opcode and type.
- OS << "unsigned FastISel::FastEmit_";
+ OS << "unsigned FastEmit_";
Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode";
+ OS << "(MVT VT, MVT RetVT, unsigned Opcode";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
}
}
-void FastISelEmitter::run(std::ostream &OS) {
+void FastISelEmitter::run(raw_ostream &OS) {
const CodeGenTarget &Target = CGP.getTargetInfo();
// Determine the target's namespace name.
EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
Target.getName() + " target", OS);
- OS << "#include \"llvm/CodeGen/FastISel.h\"\n";
- OS << "\n";
- OS << "namespace llvm {\n";
- OS << "\n";
- OS << "namespace " << InstNS.substr(0, InstNS.size() - 2) << " {\n";
- OS << "\n";
-
FastISelMap F(InstNS);
F.CollectPatterns(CGP);
- F.PrintClass(OS);
F.PrintFunctionDefinitions(OS);
-
- // Define the target FastISel creation function.
- OS << "llvm::FastISel *createFastISel(MachineFunction &mf) {\n";
- OS << " return new FastISel(mf);\n";
- OS << "}\n";
- OS << "\n";
-
- OS << "} // namespace X86\n";
- OS << "\n";
- OS << "} // namespace llvm\n";
}
FastISelEmitter::FastISelEmitter(RecordKeeper &R)
projects / oota-llvm.git / blobdiff