//
//===----------------------------------------------------------------------===//
-#ifndef CODEGEN_REGISTERS_H
-#define CODEGEN_REGISTERS_H
+#ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
+#define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
-#include "SetTheory.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SetVector.h"
-#include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/SetTheory.h"
#include <cstdlib>
+#include <list>
#include <map>
#include <set>
#include <string>
#include <vector>
+#include <deque>
namespace llvm {
class CodeGenRegBank;
std::string Namespace;
public:
+ uint16_t Size;
+ uint16_t Offset;
const unsigned EnumValue;
- unsigned LaneMask;
+ mutable unsigned LaneMask;
// Are all super-registers containing this SubRegIndex covered by their
// sub-registers?
// Returns NULL if this and Idx don't compose.
CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
CompMap::const_iterator I = Composed.find(Idx);
- return I == Composed.end() ? 0 : I->second;
+ return I == Composed.end() ? nullptr : I->second;
}
// Add a composite subreg index: this+A = B.
assert(A && B);
std::pair<CompMap::iterator, bool> Ins =
Composed.insert(std::make_pair(A, B));
- return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second;
+ // Synthetic subreg indices that aren't contiguous (for instance ARM
+ // register tuples) don't have a bit range, so it's OK to let
+ // B->Offset == -1. For the other cases, accumulate the offset and set
+ // the size here. Only do so if there is no offset yet though.
+ if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
+ (B->Offset == (uint16_t)-1)) {
+ B->Offset = Offset + A->Offset;
+ B->Size = A->Size;
+ }
+ return (Ins.second || Ins.first->second == B) ? nullptr
+ : Ins.first->second;
}
// Update the composite maps of components specified in 'ComposedOf'.
const CompMap &getComposites() const { return Composed; }
// Compute LaneMask from Composed. Return LaneMask.
- unsigned computeLaneMask();
+ unsigned computeLaneMask() const;
private:
CompMap Composed;
// Canonically ordered set.
typedef std::set<const CodeGenRegister*, Less> Set;
- // Compute the set of registers overlapping this.
- void computeOverlaps(Set &Overlaps, const CodeGenRegBank&) const;
-
private:
bool SubRegsComplete;
bool SuperRegsComplete;
// Map SubRegIndex -> sub-class. This is the largest sub-class where all
// registers have a SubRegIndex sub-register.
- DenseMap<CodeGenSubRegIndex*, CodeGenRegisterClass*> SubClassWithSubReg;
+ DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *>
+ SubClassWithSubReg;
// Map SubRegIndex -> set of super-reg classes. This is all register
// classes SuperRC such that:
//
// R:SubRegIndex in this RC for all R in SuperRC.
//
- DenseMap<CodeGenSubRegIndex*,
- SmallPtrSet<CodeGenRegisterClass*, 8> > SuperRegClasses;
+ DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>>
+ SuperRegClasses;
// Bit vector of TopoSigs for the registers in this class. This will be
// very sparse on regular architectures.
// getSubClassWithSubReg - Returns the largest sub-class where all
// registers have a SubIdx sub-register.
- CodeGenRegisterClass*
- getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
+ CodeGenRegisterClass *
+ getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
return SubClassWithSubReg.lookup(SubIdx);
}
- void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx,
+ void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
CodeGenRegisterClass *SubRC) {
SubClassWithSubReg[SubIdx] = SubRC;
}
// getSuperRegClasses - Returns a bit vector of all register classes
// containing only SubIdx super-registers of this class.
- void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
+ void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
+ BitVector &Out) const;
// addSuperRegClass - Add a class containing only SudIdx super-registers.
void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
// getSubClasses - Returns a constant BitVector of subclasses indexed by
// EnumValue.
- // The SubClasses vector includs an entry for this class.
+ // The SubClasses vector includes an entry for this class.
const BitVector &getSubClasses() const { return SubClasses; }
// getSuperClasses - Returns a list of super classes ordered by EnumValue.
unsigned SpillSize;
unsigned SpillAlignment;
- Key(const Key &O)
- : Members(O.Members),
- SpillSize(O.SpillSize),
- SpillAlignment(O.SpillAlignment) {}
-
Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0)
: Members(M), SpillSize(S), SpillAlignment(A) {}
// contain this unit.
unsigned RegClassUnitSetsIdx;
- RegUnit() : Weight(0), RegClassUnitSetsIdx(0) { Roots[0] = Roots[1] = 0; }
+ RegUnit() : Weight(0), RegClassUnitSetsIdx(0) {
+ Roots[0] = Roots[1] = nullptr;
+ }
ArrayRef<const CodeGenRegister*> getRoots() const {
assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
std::string Name;
std::vector<unsigned> Units;
+ unsigned Weight; // Cache the sum of all unit weights.
+ unsigned Order; // Cache the sort key.
+
+ RegUnitSet() : Weight(0), Order(0) {}
};
// Base vector for identifying TopoSigs. The contents uniquely identify a
class CodeGenRegBank {
SetTheory Sets;
- // SubRegIndices.
- std::vector<CodeGenSubRegIndex*> SubRegIndices;
+ std::deque<CodeGenSubRegIndex> SubRegIndices;
DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
ConcatIdxMap ConcatIdx;
// Registers.
- std::vector<CodeGenRegister*> Registers;
+ std::deque<CodeGenRegister> Registers;
StringMap<CodeGenRegister*> RegistersByName;
DenseMap<Record*, CodeGenRegister*> Def2Reg;
unsigned NumNativeRegUnits;
// already exist for a register class, we create a new entry in this vector.
std::vector<std::vector<unsigned> > RegClassUnitSets;
+ // Give each register unit set an order based on sorting criteria.
+ std::vector<unsigned> RegUnitSetOrder;
+
// Add RC to *2RC maps.
void addToMaps(CodeGenRegisterClass*);
// Sub-register indices. The first NumNamedIndices are defined by the user
// in the .td files. The rest are synthesized such that all sub-registers
// have a unique name.
- ArrayRef<CodeGenSubRegIndex*> getSubRegIndices() { return SubRegIndices; }
+ const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const {
+ return SubRegIndices;
+ }
// Find a SubRegIndex form its Record def.
CodeGenSubRegIndex *getSubRegIdx(Record*);
// Find or create a sub-register index representing the concatenation of
// non-overlapping sibling indices.
CodeGenSubRegIndex *
- getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8>&);
+ getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&);
void
- addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8> &Parts,
+ addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts,
CodeGenSubRegIndex *Idx) {
ConcatIdx.insert(std::make_pair(Parts, Idx));
}
- const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
+ const std::deque<CodeGenRegister> &getRegisters() { return Registers; }
const StringMap<CodeGenRegister*> &getRegistersByName() {
return RegistersByName;
}
// Create a native register unit that is associated with one or two root
// registers.
- unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = 0) {
+ unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) {
RegUnits.resize(RegUnits.size() + 1);
RegUnits.back().Roots[0] = R0;
RegUnits.back().Roots[1] = R1;
RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
- ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
+ std::vector<CodeGenRegisterClass *> &getRegClasses() { return RegClasses; }
+
+ const std::vector<CodeGenRegisterClass *> &getRegClasses() const {
return RegClasses;
}
return Weight;
}
+ unsigned getRegSetIDAt(unsigned Order) const {
+ return RegUnitSetOrder[Order];
+ }
+ const RegUnitSet &getRegSetAt(unsigned Order) const {
+ return RegUnitSets[RegUnitSetOrder[Order]];
+ }
+
// Increase a RegUnitWeight.
void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
getRegUnit(RUID).Weight += Inc;
unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
// Get a set of register unit IDs for a given dimension of pressure.
- RegUnitSet getRegPressureSet(unsigned Idx) const {
+ const RegUnitSet &getRegPressureSet(unsigned Idx) const {
return RegUnitSets[Idx];
}
projects / oota-llvm.git / blobdiff