#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/SetTheory.h"
#include <cstdlib>
+#include <list>
#include <map>
#include <set>
#include <string>
#include <vector>
+#include <deque>
namespace llvm {
class CodeGenRegBank;
uint16_t Size;
uint16_t Offset;
const unsigned EnumValue;
- unsigned LaneMask;
+ mutable unsigned LaneMask;
// Are all super-registers containing this SubRegIndex covered by their
// sub-registers?
const CompMap &getComposites() const { return Composed; }
// Compute LaneMask from Composed. Return LaneMask.
- unsigned computeLaneMask();
+ unsigned computeLaneMask() const;
private:
CompMap Composed;
// Map SubRegIndex -> sub-class. This is the largest sub-class where all
// registers have a SubRegIndex sub-register.
- DenseMap<CodeGenSubRegIndex*, CodeGenRegisterClass*> SubClassWithSubReg;
+ DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *>
+ SubClassWithSubReg;
// Map SubRegIndex -> set of super-reg classes. This is all register
// classes SuperRC such that:
//
// R:SubRegIndex in this RC for all R in SuperRC.
//
- DenseMap<CodeGenSubRegIndex*,
- SmallPtrSet<CodeGenRegisterClass*, 8> > SuperRegClasses;
+ DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>>
+ SuperRegClasses;
// Bit vector of TopoSigs for the registers in this class. This will be
// very sparse on regular architectures.
// getSubClassWithSubReg - Returns the largest sub-class where all
// registers have a SubIdx sub-register.
- CodeGenRegisterClass*
- getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
+ CodeGenRegisterClass *
+ getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
return SubClassWithSubReg.lookup(SubIdx);
}
- void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx,
+ void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
CodeGenRegisterClass *SubRC) {
SubClassWithSubReg[SubIdx] = SubRC;
}
// getSuperRegClasses - Returns a bit vector of all register classes
// containing only SubIdx super-registers of this class.
- void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
+ void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
+ BitVector &Out) const;
// addSuperRegClass - Add a class containing only SudIdx super-registers.
void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
class CodeGenRegBank {
SetTheory Sets;
- // SubRegIndices.
- std::vector<CodeGenSubRegIndex*> SubRegIndices;
+ std::deque<CodeGenSubRegIndex> SubRegIndices;
DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
ConcatIdxMap ConcatIdx;
// Registers.
- std::vector<CodeGenRegister*> Registers;
+ std::deque<CodeGenRegister> Registers;
StringMap<CodeGenRegister*> RegistersByName;
DenseMap<Record*, CodeGenRegister*> Def2Reg;
unsigned NumNativeRegUnits;
public:
CodeGenRegBank(RecordKeeper&);
- ~CodeGenRegBank();
SetTheory &getSets() { return Sets; }
// Sub-register indices. The first NumNamedIndices are defined by the user
// in the .td files. The rest are synthesized such that all sub-registers
// have a unique name.
- ArrayRef<CodeGenSubRegIndex*> getSubRegIndices() { return SubRegIndices; }
+ const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const {
+ return SubRegIndices;
+ }
// Find a SubRegIndex form its Record def.
CodeGenSubRegIndex *getSubRegIdx(Record*);
ConcatIdx.insert(std::make_pair(Parts, Idx));
}
- const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
+ const std::deque<CodeGenRegister> &getRegisters() { return Registers; }
const StringMap<CodeGenRegister*> &getRegistersByName() {
return RegistersByName;
}
RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
- ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
+ std::vector<CodeGenRegisterClass *> &getRegClasses() { return RegClasses; }
+
+ const std::vector<CodeGenRegisterClass *> &getRegClasses() const {
return RegClasses;
}