#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SetVector.h"
+#include "llvm/ADT/SparseBitVector.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/TableGen/Record.h"
namespace llvm {
class CodeGenRegBank;
+ /// Used to encode a step in a register lane mask transformation.
+ /// Mask the bits specified in Mask, then rotate them Rol bits to the left
+ /// assuming a wraparound at 32bits.
+ struct MaskRolPair {
+ unsigned Mask;
+ uint8_t RotateLeft;
+ bool operator==(const MaskRolPair Other) const {
+ return Mask == Other.Mask && RotateLeft == Other.RotateLeft;
+ }
+ bool operator!=(const MaskRolPair Other) const {
+ return Mask != Other.Mask || RotateLeft != Other.RotateLeft;
+ }
+ };
+
/// CodeGenSubRegIndex - Represents a sub-register index.
class CodeGenSubRegIndex {
Record *const TheDef;
uint16_t Offset;
const unsigned EnumValue;
mutable unsigned LaneMask;
+ mutable SmallVector<MaskRolPair,1> CompositionLaneMaskTransform;
// Are all super-registers containing this SubRegIndex covered by their
// sub-registers?
const std::string &getNamespace() const { return Namespace; }
std::string getQualifiedName() const;
- // Order CodeGenSubRegIndex pointers by EnumValue.
- struct Less {
- bool operator()(const CodeGenSubRegIndex *A,
- const CodeGenSubRegIndex *B) const {
- assert(A && B);
- return A->EnumValue < B->EnumValue;
- }
- };
-
// Map of composite subreg indices.
- typedef std::map<CodeGenSubRegIndex*, CodeGenSubRegIndex*, Less> CompMap;
+ typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *,
+ deref<llvm::less>> CompMap;
// Returns the subreg index that results from composing this with Idx.
// Returns NULL if this and Idx don't compose.
CompMap Composed;
};
+ inline bool operator<(const CodeGenSubRegIndex &A,
+ const CodeGenSubRegIndex &B) {
+ return A.EnumValue < B.EnumValue;
+ }
+
/// CodeGenRegister - Represents a register definition.
struct CodeGenRegister {
Record *TheDef;
unsigned EnumValue;
unsigned CostPerUse;
bool CoveredBySubRegs;
+ bool HasDisjunctSubRegs;
// Map SubRegIndex -> Register.
- typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*,
- CodeGenSubRegIndex::Less> SubRegMap;
+ typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<llvm::less>>
+ SubRegMap;
CodeGenRegister(Record *R, unsigned Enum);
}
// List of register units in ascending order.
- typedef SmallVector<unsigned, 16> RegUnitList;
+ typedef SparseBitVector<> RegUnitList;
+ typedef SmallVector<unsigned, 16> RegUnitLaneMaskList;
// How many entries in RegUnitList are native?
- unsigned NumNativeRegUnits;
+ RegUnitList NativeRegUnits;
// Get the list of register units.
// This is only valid after computeSubRegs() completes.
const RegUnitList &getRegUnits() const { return RegUnits; }
+ ArrayRef<unsigned> getRegUnitLaneMasks() const {
+ return makeArrayRef(RegUnitLaneMasks).slice(0, NativeRegUnits.count());
+ }
+
// Get the native register units. This is a prefix of getRegUnits().
- ArrayRef<unsigned> getNativeRegUnits() const {
- return makeArrayRef(RegUnits).slice(0, NumNativeRegUnits);
+ RegUnitList getNativeRegUnits() const {
+ return NativeRegUnits;
+ }
+
+ void setRegUnitLaneMasks(const RegUnitLaneMaskList &LaneMasks) {
+ RegUnitLaneMasks = LaneMasks;
}
// Inherit register units from subregisters.
bool inheritRegUnits(CodeGenRegBank &RegBank);
// Adopt a register unit for pressure tracking.
- // A unit is adopted iff its unit number is >= NumNativeRegUnits.
- void adoptRegUnit(unsigned RUID) { RegUnits.push_back(RUID); }
+ // A unit is adopted iff its unit number is >= NativeRegUnits.count().
+ void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); }
// Get the sum of this register's register unit weights.
unsigned getWeight(const CodeGenRegBank &RegBank) const;
- // Order CodeGenRegister pointers by EnumValue.
- struct Less {
- bool operator()(const CodeGenRegister *A,
- const CodeGenRegister *B) const {
- assert(A && B);
- return A->EnumValue < B->EnumValue;
- }
- };
-
// Canonically ordered set.
- typedef std::set<const CodeGenRegister*, Less> Set;
+ typedef std::vector<const CodeGenRegister*> Vec;
private:
bool SubRegsComplete;
SuperRegList SuperRegs;
DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
RegUnitList RegUnits;
+ RegUnitLaneMaskList RegUnitLaneMasks;
};
+ inline bool operator<(const CodeGenRegister &A, const CodeGenRegister &B) {
+ return A.EnumValue < B.EnumValue;
+ }
+
+ inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) {
+ return A.EnumValue == B.EnumValue;
+ }
class CodeGenRegisterClass {
- CodeGenRegister::Set Members;
+ CodeGenRegister::Vec Members;
// Allocation orders. Order[0] always contains all registers in Members.
std::vector<SmallVector<Record*, 16> > Orders;
// Bit mask of sub-classes including this, indexed by their EnumValue.
int CopyCost;
bool Allocatable;
std::string AltOrderSelect;
+ uint8_t AllocationPriority;
+ /// Contains the combination of the lane masks of all subregisters.
+ unsigned LaneMask;
+ /// True if there are at least 2 subregisters which do not interfere.
+ bool HasDisjunctSubRegs;
// Return the Record that defined this class, or NULL if the class was
// created by TableGen.
// Get the set of registers. This set contains the same registers as
// getOrder(0).
- const CodeGenRegister::Set &getMembers() const { return Members; }
+ const CodeGenRegister::Vec &getMembers() const { return Members; }
// Get a bit vector of TopoSigs present in this register class.
const BitVector &getTopoSigs() const { return TopoSigs; }
// sub-classes. Note the ordering provided by this key is not the same as
// the topological order used for the EnumValues.
struct Key {
- const CodeGenRegister::Set *Members;
+ const CodeGenRegister::Vec *Members;
unsigned SpillSize;
unsigned SpillAlignment;
- Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0)
+ Key(const CodeGenRegister::Vec *M, unsigned S = 0, unsigned A = 0)
: Members(M), SpillSize(S), SpillAlignment(A) {}
Key(const CodeGenRegisterClass &RC)
SmallVector<RegUnit, 8> RegUnits;
// Register classes.
- std::vector<CodeGenRegisterClass*> RegClasses;
+ std::list<CodeGenRegisterClass> RegClasses;
DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
RCKeyMap Key2RC;
// Create a synthetic sub-class if it is missing.
CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
- const CodeGenRegister::Set *Membs,
+ const CodeGenRegister::Vec *Membs,
StringRef Name);
// Infer missing register classes.
void computeInferredRegisterClasses();
void inferCommonSubClass(CodeGenRegisterClass *RC);
void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
- void inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
- unsigned FirstSubRegRC = 0);
+ void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) {
+ inferMatchingSuperRegClass(RC, RegClasses.begin());
+ }
+
+ void inferMatchingSuperRegClass(
+ CodeGenRegisterClass *RC,
+ std::list<CodeGenRegisterClass>::iterator FirstSubRegRC);
// Iteratively prune unit sets.
void pruneUnitSets();
void computeComposites();
// Compute a lane mask for each sub-register index.
- void computeSubRegIndexLaneMasks();
+ void computeSubRegLaneMasks();
+
+ /// Computes a lane mask for each register unit enumerated by a physical
+ /// register.
+ void computeRegUnitLaneMasks();
public:
CodeGenRegBank(RecordKeeper&);
RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
- std::vector<CodeGenRegisterClass *> &getRegClasses() { return RegClasses; }
+ std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }
- const std::vector<CodeGenRegisterClass *> &getRegClasses() const {
+ const std::list<CodeGenRegisterClass> &getRegClasses() const {
return RegClasses;
}
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