//
//===----------------------------------------------------------------------===//
-#include "CodeEmitterGen.h"
#include "CodeGenTarget.h"
-#include "Record.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
#include <map>
+#include <string>
+#include <vector>
using namespace llvm;
// FIXME: Somewhat hackish to use a command line option for this. There should
cl::desc("Generate CodeEmitter for use with the MC library."),
cl::init(false));
-void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
- for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
- I != E; ++I) {
- Record *R = *I;
- if (R->getValueAsString("Namespace") == "TargetOpcode" ||
- R->getValueAsBit("isPseudo"))
- continue;
+namespace {
- BitsInit *BI = R->getValueAsBitsInit("Inst");
+class CodeEmitterGen {
+ RecordKeeper &Records;
+public:
+ CodeEmitterGen(RecordKeeper &R) : Records(R) {}
- unsigned numBits = BI->getNumBits();
-
- SmallVector<Init *, 16> NewBits(numBits);
-
- for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
- unsigned bitSwapIdx = numBits - bit - 1;
- Init *OrigBit = BI->getBit(bit);
- Init *BitSwap = BI->getBit(bitSwapIdx);
- NewBits[bit] = BitSwap;
- NewBits[bitSwapIdx] = OrigBit;
- }
- if (numBits % 2) {
- unsigned middle = (numBits + 1) / 2;
- NewBits[middle] = BI->getBit(middle);
- }
+ void run(raw_ostream &o);
+private:
+ int getVariableBit(const std::string &VarName, BitsInit *BI, int bit);
+ std::string getInstructionCase(Record *R, CodeGenTarget &Target);
+ void AddCodeToMergeInOperand(Record *R, BitsInit *BI,
+ const std::string &VarName,
+ unsigned &NumberedOp,
+ std::set<unsigned> &NamedOpIndices,
+ std::string &Case, CodeGenTarget &Target);
- BitsInit *NewBI = BitsInit::get(NewBits);
-
- // Update the bits in reversed order so that emitInstrOpBits will get the
- // correct endianness.
- R->getValue("Inst")->setValue(NewBI);
- }
-}
+};
// If the VarBitInit at position 'bit' matches the specified variable then
// return the variable bit position. Otherwise return -1.
int CodeEmitterGen::getVariableBit(const std::string &VarName,
BitsInit *BI, int bit) {
- if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) {
- if (VarInit *VI = dynamic_cast<VarInit*>(VBI->getVariable()))
+ if (VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(bit))) {
+ if (VarInit *VI = dyn_cast<VarInit>(VBI->getBitVar()))
if (VI->getName() == VarName)
return VBI->getBitNum();
- } else if (VarInit *VI = dynamic_cast<VarInit*>(BI->getBit(bit))) {
+ } else if (VarInit *VI = dyn_cast<VarInit>(BI->getBit(bit))) {
if (VI->getName() == VarName)
return 0;
}
void CodeEmitterGen::
AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
unsigned &NumberedOp,
+ std::set<unsigned> &NamedOpIndices,
std::string &Case, CodeGenTarget &Target) {
CodeGenInstruction &CGI = Target.getInstruction(R);
assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
"Explicitly used operand also marked as not emitted!");
} else {
+ unsigned NumberOps = CGI.Operands.size();
/// If this operand is not supposed to be emitted by the
/// generated emitter, skip it.
- while (CGI.Operands.isFlatOperandNotEmitted(NumberedOp))
+ while (NumberedOp < NumberOps &&
+ (CGI.Operands.isFlatOperandNotEmitted(NumberedOp) ||
+ (NamedOpIndices.size() && NamedOpIndices.count(
+ CGI.Operands.getSubOperandNumber(NumberedOp).first)))) {
++NumberedOp;
+
+ if (NumberedOp >= CGI.Operands.back().MIOperandNo +
+ CGI.Operands.back().MINumOperands) {
+ errs() << "Too few operands in record " << R->getName() <<
+ " (no match for variable " << VarName << "):\n";
+ errs() << *R;
+ errs() << '\n';
+
+ return;
+ }
+ }
+
OpIdx = NumberedOp++;
}
Case += " // op: " + VarName + "\n" +
" op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
if (MCEmitter)
- Case += ", Fixups";
+ Case += ", Fixups, STI";
Case += ");\n";
}
} else {
Case += " // op: " + VarName + "\n" +
" op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
if (MCEmitter)
- Case += ", Fixups";
+ Case += ", Fixups, STI";
Case += ");\n";
}
--bit;
}
- unsigned opMask = ~0U >> (32-N);
+ uint64_t opMask = ~(uint64_t)0 >> (64-N);
int opShift = beginVarBit - N + 1;
opMask <<= opShift;
opShift = beginInstBit - beginVarBit;
if (opShift > 0) {
- Case += " Value |= (op & " + utostr(opMask) + "U) << " +
+ Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) << " +
itostr(opShift) + ";\n";
} else if (opShift < 0) {
- Case += " Value |= (op & " + utostr(opMask) + "U) >> " +
+ Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) >> " +
itostr(-opShift) + ";\n";
} else {
- Case += " Value |= op & " + utostr(opMask) + "U;\n";
+ Case += " Value |= op & UINT64_C(" + utostr(opMask) + ");\n";
}
}
}
const std::vector<RecordVal> &Vals = R->getValues();
unsigned NumberedOp = 0;
+ std::set<unsigned> NamedOpIndices;
+ // Collect the set of operand indices that might correspond to named
+ // operand, and skip these when assigning operands based on position.
+ if (Target.getInstructionSet()->
+ getValueAsBit("noNamedPositionallyEncodedOperands")) {
+ CodeGenInstruction &CGI = Target.getInstruction(R);
+ for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
+ unsigned OpIdx;
+ if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx))
+ continue;
+
+ NamedOpIndices.insert(OpIdx);
+ }
+ }
+
// Loop over all of the fields in the instruction, determining which are the
// operands to the instruction.
for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete())
continue;
- AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp, Case, Target);
+ AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp,
+ NamedOpIndices, Case, Target);
}
std::string PostEmitter = R->getValueAsString("PostEncoderMethod");
- if (!PostEmitter.empty())
- Case += " Value = " + PostEmitter + "(MI, Value);\n";
+ if (!PostEmitter.empty()) {
+ Case += " Value = " + PostEmitter + "(MI, Value";
+ if (MCEmitter)
+ Case += ", STI";
+ Case += ");\n";
+ }
return Case;
}
std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
// For little-endian instruction bit encodings, reverse the bit order
- if (Target.isLittleEndianEncoding()) reverseBits(Insts);
-
- EmitSourceFileHeader("Machine Code Emitter", o);
+ Target.reverseBitsForLittleEndianEncoding();
const std::vector<const CodeGenInstruction*> &NumberedInstructions =
Target.getInstructionsByEnumValue();
// Emit function declaration
- o << "unsigned " << Target.getName();
+ o << "uint64_t " << Target.getName();
if (MCEmitter)
o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
- << " SmallVectorImpl<MCFixup> &Fixups) const {\n";
+ << " SmallVectorImpl<MCFixup> &Fixups,\n"
+ << " const MCSubtargetInfo &STI) const {\n";
else
o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n";
// Emit instruction base values
- o << " static const unsigned InstBits[] = {\n";
+ o << " static const uint64_t InstBits[] = {\n";
for (std::vector<const CodeGenInstruction*>::const_iterator
IN = NumberedInstructions.begin(),
EN = NumberedInstructions.end();
if (R->getValueAsString("Namespace") == "TargetOpcode" ||
R->getValueAsBit("isPseudo")) {
- o << " 0U,\n";
+ o << " UINT64_C(0),\n";
continue;
}
BitsInit *BI = R->getValueAsBitsInit("Inst");
// Start by filling in fixed values.
- unsigned Value = 0;
+ uint64_t Value = 0;
for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
- if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1)))
- Value |= B->getValue() << (e-i-1);
+ if (BitInit *B = dyn_cast<BitInit>(BI->getBit(e-i-1)))
+ Value |= (uint64_t)B->getValue() << (e-i-1);
}
- o << " " << Value << "U," << '\t' << "// " << R->getName() << "\n";
+ o << " UINT64_C(" << Value << ")," << '\t' << "// " << R->getName() << "\n";
}
- o << " 0U\n };\n";
+ o << " UINT64_C(0)\n };\n";
// Map to accumulate all the cases.
std::map<std::string, std::vector<std::string> > CaseMap;
// Emit initial function code
o << " const unsigned opcode = MI.getOpcode();\n"
- << " unsigned Value = InstBits[opcode];\n"
- << " unsigned op = 0;\n"
+ << " uint64_t Value = InstBits[opcode];\n"
+ << " uint64_t op = 0;\n"
<< " (void)op; // suppress warning\n"
<< " switch (opcode) {\n";
// Default case: unhandled opcode
o << " default:\n"
- << " std::string msg;\n"
- << " raw_string_ostream Msg(msg);\n"
+ << " string_ostream Msg;\n"
<< " Msg << \"Not supported instr: \" << MI;\n"
<< " report_fatal_error(Msg.str());\n"
<< " }\n"
<< " return Value;\n"
<< "}\n\n";
}
+
+} // End anonymous namespace
+
+namespace llvm {
+
+void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) {
+ emitSourceFileHeader("Machine Code Emitter", OS);
+ CodeEmitterGen(RK).run(OS);
+}
+
+} // End llvm namespace
projects / oota-llvm.git / blobdiff