[InstCombine] Move SSE2/AVX2 arithmetic vector shift folding to instcombiner

[oota-llvm.git] / test / Transforms / InstCombine / x86-vector-shifts.ll

diff --git a/test/Transforms/InstCombine/x86-vector-shifts.ll b/test/Transforms/InstCombine/x86-vector-shifts.ll
index fdfad4900f972fae9a26efcd47afb7593be29762..95700f08d810fe4733471a22d56a1c8fe6eefb26 100644 (file)
--- a/test/Transforms/InstCombine/x86-vector-shifts.ll
+++ b/test/Transforms/InstCombine/x86-vector-shifts.ll
@@ -1,6 +1,102 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s\r
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"\r
 \r
+;\r
+; ASHR - Immediate\r
+;\r
+\r
+define <8 x i16> @sse2_psrai_w_0(<8 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psrai_w_0\r
+; CHECK-NEXT: ret <8 x i16> %v\r
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %v, i32 0)\r
+  ret <8 x i16> %1\r
+}\r
+\r
+define <8 x i16> @sse2_psrai_w_15(<8 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psrai_w_15\r
+; CHECK-NEXT: %1 = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <8 x i16> %1\r
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %v, i32 15)\r
+  ret <8 x i16> %1\r
+}\r
+\r
+define <8 x i16> @sse2_psrai_w_64(<8 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psrai_w_64\r
+; CHECK-NEXT: %1 = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <8 x i16> %1\r
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %v, i32 64)\r
+  ret <8 x i16> %1\r
+}\r
+\r
+define <4 x i32> @sse2_psrai_d_0(<4 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psrai_d_0\r
+; CHECK-NEXT: ret <4 x i32> %v\r
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %v, i32 0)\r
+  ret <4 x i32> %1\r
+}\r
+\r
+define <4 x i32> @sse2_psrai_d_15(<4 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psrai_d_15\r
+; CHECK-NEXT: %1 = ashr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>\r
+; CHECK-NEXT: ret <4 x i32> %1\r
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %v, i32 15)\r
+  ret <4 x i32> %1\r
+}\r
+\r
+define <4 x i32> @sse2_psrai_d_64(<4 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psrai_d_64\r
+; CHECK-NEXT: %1 = ashr <4 x i32> %v, <i32 31, i32 31, i32 31, i32 31>\r
+; CHECK-NEXT: ret <4 x i32> %1\r
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %v, i32 64)\r
+  ret <4 x i32> %1\r
+}\r
+\r
+define <16 x i16> @avx2_psrai_w_0(<16 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psrai_w_0\r
+; CHECK-NEXT: ret <16 x i16> %v\r
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %v, i32 0)\r
+  ret <16 x i16> %1\r
+}\r
+\r
+define <16 x i16> @avx2_psrai_w_15(<16 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psrai_w_15\r
+; CHECK-NEXT: %1 = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <16 x i16> %1\r
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %v, i32 15)\r
+  ret <16 x i16> %1\r
+}\r
+\r
+define <16 x i16> @avx2_psrai_w_64(<16 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psrai_w_64\r
+; CHECK-NEXT: %1 = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <16 x i16> %1\r
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %v, i32 64)\r
+  ret <16 x i16> %1\r
+}\r
+\r
+define <8 x i32> @avx2_psrai_d_0(<8 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psrai_d_0\r
+; CHECK-NEXT: ret <8 x i32> %v\r
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %v, i32 0)\r
+  ret <8 x i32> %1\r
+}\r
+\r
+define <8 x i32> @avx2_psrai_d_15(<8 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psrai_d_15\r
+; CHECK-NEXT: %1 = ashr <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>\r
+; CHECK-NEXT: ret <8 x i32> %1\r
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %v, i32 15)\r
+  ret <8 x i32> %1\r
+}\r
+\r
+define <8 x i32> @avx2_psrai_d_64(<8 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psrai_d_64\r
+; CHECK-NEXT: %1 = ashr <8 x i32> %v, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>\r
+; CHECK-NEXT: ret <8 x i32> %1\r
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %v, i32 64)\r
+  ret <8 x i32> %1\r
+}\r
+\r
 ;\r
 ; LSHR - Immediate\r
 ;\r
@@ -273,6 +369,134 @@ define <4 x i64> @avx2_pslli_q_64(<4 x i64> %v) nounwind readnone uwtable {
   ret <4 x i64> %1\r
 }\r
 \r
+;\r
+; ASHR - Constant Vector\r
+;\r
+\r
+define <8 x i16> @sse2_psra_w_0(<8 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psra_w_0\r
+; CHECK-NEXT: ret <8 x i16> %v\r
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> zeroinitializer)\r
+  ret <8 x i16> %1\r
+}\r
+\r
+define <8 x i16> @sse2_psra_w_15(<8 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psra_w_15\r
+; CHECK-NEXT: %1 = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <8 x i16> %1\r
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)\r
+  ret <8 x i16> %1\r
+}\r
+\r
+define <8 x i16> @sse2_psra_w_15_splat(<8 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psra_w_15_splat\r
+; CHECK-NEXT: %1 = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <8 x i16> %1\r
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)\r
+  ret <8 x i16> %1\r
+}\r
+\r
+define <8 x i16> @sse2_psra_w_64(<8 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psra_w_64\r
+; CHECK-NEXT: %1 = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <8 x i16> %1\r
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)\r
+  ret <8 x i16> %1\r
+}\r
+\r
+define <4 x i32> @sse2_psra_d_0(<4 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psra_d_0\r
+; CHECK-NEXT: ret <4 x i32> %v\r
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> zeroinitializer)\r
+  ret <4 x i32> %1\r
+}\r
+\r
+define <4 x i32> @sse2_psra_d_15(<4 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psra_d_15\r
+; CHECK-NEXT: %1 = ashr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>\r
+; CHECK-NEXT: ret <4 x i32> %1\r
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)\r
+  ret <4 x i32> %1\r
+}\r
+\r
+define <4 x i32> @sse2_psra_d_15_splat(<4 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psra_d_15_splat\r
+; CHECK-NEXT: %1 = ashr <4 x i32> %v, <i32 31, i32 31, i32 31, i32 31>\r
+; CHECK-NEXT: ret <4 x i32> %1\r
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)\r
+  ret <4 x i32> %1\r
+}\r
+\r
+define <4 x i32> @sse2_psra_d_64(<4 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @sse2_psra_d_64\r
+; CHECK-NEXT: %1 = ashr <4 x i32> %v, <i32 31, i32 31, i32 31, i32 31>\r
+; CHECK-NEXT: ret <4 x i32> %1\r
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)\r
+  ret <4 x i32> %1\r
+}\r
+\r
+define <16 x i16> @avx2_psra_w_0(<16 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psra_w_0\r
+; CHECK-NEXT: ret <16 x i16> %v\r
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16> zeroinitializer)\r
+  ret <16 x i16> %1\r
+}\r
+\r
+define <16 x i16> @avx2_psra_w_15(<16 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psra_w_15\r
+; CHECK-NEXT: %1 = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <16 x i16> %1\r
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)\r
+  ret <16 x i16> %1\r
+}\r
+\r
+define <16 x i16> @avx2_psra_w_15_splat(<16 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psra_w_15_splat\r
+; CHECK-NEXT: %1 = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <16 x i16> %1\r
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)\r
+  ret <16 x i16> %1\r
+}\r
+\r
+define <16 x i16> @avx2_psra_w_64(<16 x i16> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psra_w_64\r
+; CHECK-NEXT: %1 = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>\r
+; CHECK-NEXT: ret <16 x i16> %1\r
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)\r
+  ret <16 x i16> %1\r
+}\r
+\r
+define <8 x i32> @avx2_psra_d_0(<8 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psra_d_0\r
+; CHECK-NEXT: ret <8 x i32> %v\r
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> zeroinitializer)\r
+  ret <8 x i32> %1\r
+}\r
+\r
+define <8 x i32> @avx2_psra_d_15(<8 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psra_d_15\r
+; CHECK-NEXT: %1 = ashr <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>\r
+; CHECK-NEXT: ret <8 x i32> %1\r
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)\r
+  ret <8 x i32> %1\r
+}\r
+\r
+define <8 x i32> @avx2_psra_d_15_splat(<8 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psra_d_15_splat\r
+; CHECK-NEXT: %1 = ashr <8 x i32> %v, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>\r
+; CHECK-NEXT: ret <8 x i32> %1\r
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)\r
+  ret <8 x i32> %1\r
+}\r
+\r
+define <8 x i32> @avx2_psra_d_64(<8 x i32> %v) nounwind readnone uwtable {\r
+; CHECK-LABEL: @avx2_psra_d_64\r
+; CHECK-NEXT: %1 = ashr <8 x i32> %v, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>\r
+; CHECK-NEXT: ret <8 x i32> %1\r
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)\r
+  ret <8 x i32> %1\r
+}\r
+\r
 ;\r
 ; LSHR - Constant Vector\r
 ;\r
@@ -605,6 +829,82 @@ define <4 x i64> @avx2_psll_q_64(<4 x i64> %v) nounwind readnone uwtable {
 ; Constant Folding\r
 ;\r
 \r
+define <8 x i16> @test_sse2_psra_w_0(<8 x i16> %A) {\r
+; CHECK-LABEL: @test_sse2_psra_w_0\r
+; CHECK-NEXT: ret <8 x i16> %A\r
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %A, i32 0)\r
+  %2 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %1, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 7, i16 0, i16 0, i16 0>)\r
+  %3 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %2, i32 0)\r
+  ret <8 x i16> %3\r
+}\r
+\r
+define <8 x i16> @test_sse2_psra_w_8() {\r
+; CHECK-LABEL: @test_sse2_psra_w_8\r
+; CHECK-NEXT: ret <8 x i16> <i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16>\r
+  %1 = bitcast <2 x i64> <i64 1152956690052710400, i64 1152956690052710400> to <8 x i16>\r
+  %2 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %1, i32 3)\r
+  %3 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %2, <8 x i16> <i16 3, i16 0, i16 0, i16 0, i16 7, i16 0, i16 0, i16 0>)\r
+  %4 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %3, i32 2)\r
+  ret <8 x i16> %4\r
+}\r
+\r
+define <4 x i32> @test_sse2_psra_d_0(<4 x i32> %A) {\r
+; CHECK-LABEL: @test_sse2_psra_d_0\r
+; CHECK-NEXT: ret <4 x i32> %A\r
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %A, i32 0)\r
+  %2 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %1, <4 x i32> <i32 0, i32 0, i32 7, i32 0>)\r
+  %3 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %1, i32 0)\r
+  ret <4 x i32> %3\r
+}\r
+\r
+define <4 x i32> @sse2_psra_d_8() {\r
+; CHECK-LABEL: @sse2_psra_d_8\r
+; CHECK-NEXT: ret <4 x i32> <i32 4194432, i32 1048608, i32 4194432, i32 1048608>\r
+  %1 = bitcast <2 x i64> <i64 1152956690052710400, i64 1152956690052710400> to <4 x i32>\r
+  %2 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %1, i32 3)\r
+  %3 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %2, <4 x i32> <i32 3, i32 0, i32 7, i32 0>)\r
+  %4 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %3, i32 2)\r
+  ret <4 x i32> %4\r
+}\r
+\r
+define <16 x i16> @test_avx2_psra_w_0(<16 x i16> %A) {\r
+; CHECK-LABEL: @test_avx2_psra_w_0\r
+; CHECK-NEXT: ret <16 x i16> %A\r
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %A, i32 0)\r
+  %2 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %1, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 7, i16 0, i16 0, i16 0>)\r
+  %3 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %2, i32 0)\r
+  ret <16 x i16> %3\r
+}\r
+\r
+define <16 x i16> @test_avx2_psra_w_8(<16 x i16> %A) {\r
+; CHECK-LABEL: @test_avx2_psra_w_8\r
+; CHECK-NEXT: ret <16 x i16> <i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16>\r
+  %1 = bitcast <4 x i64> <i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400> to <16 x i16>\r
+  %2 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %1, i32 3)\r
+  %3 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %2, <8 x i16> <i16 3, i16 0, i16 0, i16 0, i16 7, i16 0, i16 0, i16 0>)\r
+  %4 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %3, i32 2)\r
+  ret <16 x i16> %4\r
+}\r
+\r
+define <8 x i32> @test_avx2_psra_d_0(<8 x i32> %A) {\r
+; CHECK-LABEL: @test_avx2_psra_d_0\r
+; CHECK-NEXT: ret <8 x i32> %A\r
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %A, i32 0)\r
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %1, <4 x i32> <i32 0, i32 0, i32 7, i32 0>)\r
+  %3 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %2, i32 0)\r
+  ret <8 x i32> %3\r
+}\r
+\r
+define <8 x i32> @test_avx2_psra_d_8() {\r
+; CHECK-LABEL: @test_avx2_psra_d_8\r
+; CHECK-NEXT: ret <8 x i32> <i32 4194432, i32 1048608, i32 4194432, i32 1048608, i32 4194432, i32 1048608, i32 4194432, i32 1048608>\r
+  %1 = bitcast <4 x i64> <i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400> to <8 x i32>\r
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %1, i32 3)\r
+  %3 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %2, <4 x i32> <i32 3, i32 0, i32 7, i32 0>)\r
+  %4 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %3, i32 2)\r
+  ret <8 x i32> %4\r
+}\r
+\r
 define <2 x i64> @test_sse2_1() nounwind readnone uwtable {\r
   %S = bitcast i32 1 to i32\r
   %1 = zext i32 %S to i64\r
@@ -814,4 +1114,13 @@ declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) #1
 declare <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32>, <4 x i32>) #1\r
 declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) #1\r
 \r
+declare <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32>, i32) #1\r
+declare <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16>, i32) #1\r
+declare <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32>, <4 x i32>) #1\r
+declare <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16>, <8 x i16>) #1\r
+declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32) #1\r
+declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) #1\r
+declare <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32>, <4 x i32>) #1\r
+declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) #1\r
+\r
 attributes #1 = { nounwind readnone }\r