Update Transforms tests to use CHECK-LABEL for easier debugging. No functionality...

[oota-llvm.git] / test / Transforms / InstCombine / vector-mul.ll

diff --git a/test/Transforms/InstCombine/vector-mul.ll b/test/Transforms/InstCombine/vector-mul.ll
index 4e4417f93c0f4dde6ed9a620450186b5f6e46a2f..284d407ce33f1a149b2d6493af5aa6734cdea86d 100644 (file)
--- a/test/Transforms/InstCombine/vector-mul.ll
+++ b/test/Transforms/InstCombine/vector-mul.ll
@@ -9,7 +9,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @Zero_i8
+; CHECK-LABEL: @Zero_i8(
 ; CHECK: ret <4 x i8> zeroinitializer
 
 define <4 x i8> @Identity_i8(<4 x i8> %InVec)  {
@@ -18,7 +18,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @Identity_i8
+; CHECK-LABEL: @Identity_i8(
 ; CHECK: ret <4 x i8> %InVec
 
 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec)  {
@@ -27,7 +27,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @AddToSelf_i8
+; CHECK-LABEL: @AddToSelf_i8(
 ; CHECK: shl <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
 ; CHECK: ret
 
@@ -37,7 +37,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @SplatPow2Test1_i8
+; CHECK-LABEL: @SplatPow2Test1_i8(
 ; CHECK: shl <4 x i8> %InVec, <i8 2, i8 2, i8 2, i8 2>
 ; CHECK: ret
 
@@ -47,7 +47,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @SplatPow2Test2_i8
+; CHECK-LABEL: @SplatPow2Test2_i8(
 ; CHECK: shl <4 x i8> %InVec, <i8 3, i8 3, i8 3, i8 3>
 ; CHECK: ret
 
@@ -57,7 +57,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @MulTest1_i8
+; CHECK-LABEL: @MulTest1_i8(
 ; CHECK: shl <4 x i8> %InVec, <i8 0, i8 1, i8 2, i8 3>
 ; CHECK: ret
 
@@ -67,7 +67,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @MulTest2_i8
+; CHECK-LABEL: @MulTest2_i8(
 ; CHECK: mul <4 x i8> %InVec, <i8 3, i8 3, i8 3, i8 3>
 ; CHECK: ret
 
@@ -77,7 +77,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @MulTest3_i8
+; CHECK-LABEL: @MulTest3_i8(
 ; CHECK: shl <4 x i8> %InVec, <i8 2, i8 2, i8 1, i8 1>
 ; CHECK: ret
 
@@ -88,7 +88,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @MulTest4_i8
+; CHECK-LABEL: @MulTest4_i8(
 ; CHECK: mul <4 x i8> %InVec, <i8 4, i8 4, i8 0, i8 1>
 ; CHECK: ret
 
@@ -98,7 +98,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @Zero_i16
+; CHECK-LABEL: @Zero_i16(
 ; CHECK: ret <4 x i16> zeroinitializer
 
 define <4 x i16> @Identity_i16(<4 x i16> %InVec)  {
@@ -107,7 +107,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @Identity_i16
+; CHECK-LABEL: @Identity_i16(
 ; CHECK: ret <4 x i16> %InVec
 
 define <4 x i16> @AddToSelf_i16(<4 x i16> %InVec)  {
@@ -116,7 +116,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @AddToSelf_i16
+; CHECK-LABEL: @AddToSelf_i16(
 ; CHECK: shl <4 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1>
 ; CHECK: ret
 
@@ -126,7 +126,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @SplatPow2Test1_i16
+; CHECK-LABEL: @SplatPow2Test1_i16(
 ; CHECK: shl <4 x i16> %InVec, <i16 2, i16 2, i16 2, i16 2>
 ; CHECK: ret
 
@@ -136,7 +136,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @SplatPow2Test2_i16
+; CHECK-LABEL: @SplatPow2Test2_i16(
 ; CHECK: shl <4 x i16> %InVec, <i16 3, i16 3, i16 3, i16 3>
 ; CHECK: ret
 
@@ -146,7 +146,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @MulTest1_i16
+; CHECK-LABEL: @MulTest1_i16(
 ; CHECK: shl <4 x i16> %InVec, <i16 0, i16 1, i16 2, i16 3>
 ; CHECK: ret
 
@@ -156,7 +156,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @MulTest2_i16
+; CHECK-LABEL: @MulTest2_i16(
 ; CHECK: mul <4 x i16> %InVec, <i16 3, i16 3, i16 3, i16 3>
 ; CHECK: ret
 
@@ -166,7 +166,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @MulTest3_i16
+; CHECK-LABEL: @MulTest3_i16(
 ; CHECK: shl <4 x i16> %InVec, <i16 2, i16 2, i16 1, i16 1>
 ; CHECK: ret
 
@@ -176,7 +176,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @MulTest4_i16
+; CHECK-LABEL: @MulTest4_i16(
 ; CHECK: mul <4 x i16> %InVec, <i16 4, i16 4, i16 0, i16 2>
 ; CHECK: ret
 
@@ -186,7 +186,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @Zero_i32
+; CHECK-LABEL: @Zero_i32(
 ; CHECK: ret <4 x i32> zeroinitializer
 
 define <4 x i32> @Identity_i32(<4 x i32> %InVec)  {
@@ -195,7 +195,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @Identity_i32
+; CHECK-LABEL: @Identity_i32(
 ; CHECK: ret <4 x i32> %InVec
 
 define <4 x i32> @AddToSelf_i32(<4 x i32> %InVec)  {
@@ -204,7 +204,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @AddToSelf_i32
+; CHECK-LABEL: @AddToSelf_i32(
 ; CHECK: shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
 ; CHECK: ret
 
@@ -215,7 +215,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @SplatPow2Test1_i32
+; CHECK-LABEL: @SplatPow2Test1_i32(
 ; CHECK: shl <4 x i32> %InVec, <i32 2, i32 2, i32 2, i32 2>
 ; CHECK: ret
 
@@ -225,7 +225,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @SplatPow2Test2_i32
+; CHECK-LABEL: @SplatPow2Test2_i32(
 ; CHECK: shl <4 x i32> %InVec, <i32 3, i32 3, i32 3, i32 3>
 ; CHECK: ret
 
@@ -235,7 +235,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @MulTest1_i32
+; CHECK-LABEL: @MulTest1_i32(
 ; CHECK: shl <4 x i32> %InVec, <i32 0, i32 1, i32 2, i32 3>
 ; CHECK: ret
 
@@ -245,7 +245,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @MulTest2_i32
+; CHECK-LABEL: @MulTest2_i32(
 ; CHECK: mul <4 x i32> %InVec, <i32 3, i32 3, i32 3, i32 3>
 ; CHECK: ret
 
@@ -255,7 +255,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @MulTest3_i32
+; CHECK-LABEL: @MulTest3_i32(
 ; CHECK: shl <4 x i32> %InVec, <i32 2, i32 2, i32 1, i32 1>
 ; CHECK: ret
 
@@ -266,7 +266,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @MulTest4_i32
+; CHECK-LABEL: @MulTest4_i32(
 ; CHECK: mul <4 x i32> %InVec, <i32 4, i32 4, i32 0, i32 1>
 ; CHECK: ret
 
@@ -276,7 +276,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @Zero_i64
+; CHECK-LABEL: @Zero_i64(
 ; CHECK: ret <4 x i64> zeroinitializer
 
 define <4 x i64> @Identity_i64(<4 x i64> %InVec)  {
@@ -285,7 +285,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @Identity_i64
+; CHECK-LABEL: @Identity_i64(
 ; CHECK: ret <4 x i64> %InVec
 
 define <4 x i64> @AddToSelf_i64(<4 x i64> %InVec)  {
@@ -294,7 +294,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @AddToSelf_i64
+; CHECK-LABEL: @AddToSelf_i64(
 ; CHECK: shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
 ; CHECK: ret
 
@@ -304,7 +304,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @SplatPow2Test1_i64
+; CHECK-LABEL: @SplatPow2Test1_i64(
 ; CHECK: shl <4 x i64> %InVec, <i64 2, i64 2, i64 2, i64 2>
 ; CHECK: ret
 
@@ -314,7 +314,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @SplatPow2Test2_i64
+; CHECK-LABEL: @SplatPow2Test2_i64(
 ; CHECK: shl <4 x i64> %InVec, <i64 3, i64 3, i64 3, i64 3>
 ; CHECK: ret
 
@@ -324,7 +324,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @MulTest1_i64
+; CHECK-LABEL: @MulTest1_i64(
 ; CHECK: shl <4 x i64> %InVec, <i64 0, i64 1, i64 2, i64 3>
 ; CHECK: ret
 
@@ -334,7 +334,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @MulTest2_i64
+; CHECK-LABEL: @MulTest2_i64(
 ; CHECK: mul <4 x i64> %InVec, <i64 3, i64 3, i64 3, i64 3>
 ; CHECK: ret
 
@@ -344,7 +344,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @MulTest3_i64
+; CHECK-LABEL: @MulTest3_i64(
 ; CHECK: shl <4 x i64> %InVec, <i64 2, i64 2, i64 1, i64 1>
 ; CHECK: ret
 
@@ -354,7 +354,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @MulTest4_i64
+; CHECK-LABEL: @MulTest4_i64(
 ; CHECK: mul <4 x i64> %InVec, <i64 4, i64 4, i64 0, i64 1>
 ; CHECK: ret
 
@@ -369,7 +369,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @ShiftMulTest1
+; CHECK-LABEL: @ShiftMulTest1(
 ; CHECK: mul <4 x i8> %InVec, <i8 12, i8 12, i8 12, i8 12>
 ; CHECK: ret
 
@@ -380,7 +380,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @ShiftMulTest2
+; CHECK-LABEL: @ShiftMulTest2(
 ; CHECK: mul <4 x i16> %InVec, <i16 12, i16 12, i16 12, i16 12>
 ; CHECK: ret
 
@@ -391,7 +391,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @ShiftMulTest3
+; CHECK-LABEL: @ShiftMulTest3(
 ; CHECK: mul <4 x i32> %InVec, <i32 12, i32 12, i32 12, i32 12>
 ; CHECK: ret
 
@@ -402,7 +402,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @ShiftMulTest4
+; CHECK-LABEL: @ShiftMulTest4(
 ; CHECK: mul <4 x i64> %InVec, <i64 12, i64 12, i64 12, i64 12>
 ; CHECK: ret