InstCombine: Don't assume that m_ZExt matches an Instruction

[oota-llvm.git] / test / TableGen / list-element-bitref.td

diff --git a/test/TableGen/list-element-bitref.td b/test/TableGen/list-element-bitref.td
index 02607bdcd5efb52c873b2fe4c8a086fcc013e2d7..0f59b537fa6d6ffbb9b67df7670fccf680078e21 100644 (file)
--- a/test/TableGen/list-element-bitref.td
+++ b/test/TableGen/list-element-bitref.td
@@ -1,6 +1,7 @@
 // RUN: llvm-tblgen %s | FileCheck %s
+// XFAIL: vg_leak
 
-class C<list<bits<8>> L> {
+class C<list<bits<4>> L> {
   bits<2> V0 = L[0]{1-0};
   bits<2> V1 = L[1]{3-2};
   string V2 = !if(L[0]{0}, "Odd", "Even");
@@ -9,6 +10,6 @@ class C<list<bits<8>> L> {
 def c0 : C<[0b0101, 0b1010]>;
 
 // CHECK: def c0
-// CHECk-NEXT: bits<2> V0 = { 0, 1 };
-// CHECk-NEXT: bits<2> V1 = { 1, 0 };
-// CHECk-NEXT: string V2 = "Odd";
+// CHECK-NEXT: bits<2> V0 = { 0, 1 };
+// CHECK-NEXT: bits<2> V1 = { 1, 0 };
+// CHECK-NEXT: string V2 = "Odd";