[Hexagon] Adding transfers to and from control registers.

[oota-llvm.git] / test / MC / Disassembler / Hexagon / cr.txt

diff --git a/test/MC/Disassembler/Hexagon/cr.txt b/test/MC/Disassembler/Hexagon/cr.txt
index 9957e6fd74461f59ff7b9cadd7d9f3813ab23da7..e72ec9f6d62dc36bd7c2fd513561abde54047360 100644 (file)
--- a/test/MC/Disassembler/Hexagon/cr.txt
+++ b/test/MC/Disassembler/Hexagon/cr.txt
@@ -4,6 +4,26 @@
 # CHECK: p1 = any8(p2)
 0x01 0xc0 0xa2 0x6b
 # CHECK: p1 = all8(p2)
+0x08 0xc4 0x15 0x60
+# CHECK: loop0
+0x08 0xc4 0x35 0x60
+# CHECK: loop1
+0x68 0xc4 0x00 0x69
+# CHECK: loop0
+0x68 0xc4 0x20 0x69
+# CHECK: loop1
+0x08 0xc4 0xb5 0x60
+# CHECK: p3 = sp1loop0
+0x08 0xc4 0xd5 0x60
+# CHECK: p3 = sp2loop0
+0x08 0xc4 0xf5 0x60
+# CHECK: p3 = sp3loop0
+0xa9 0xc4 0xa0 0x69
+# CHECK: p3 = sp1loop0
+0xa9 0xc4 0xc0 0x69
+# CHECK: p3 = sp2loop0
+0xa9 0xc4 0xe0 0x69
+# CHECK: p3 = sp3loop0
 0x01 0xc3 0x02 0x6b
 # CHECK: p1 = and(p3, p2)
 0x01 0xc3 0x62 0x6b
@@ -15,4 +35,8 @@
 0x01 0xc0 0xc2 0x6b
 # CHECK: p1 = not(p2)
 0x01 0xc2 0x43 0x6b
-# CHECK: p1 = xor(p3, p2)
\ No newline at end of file
+# CHECK: p1 = xor(p3, p2)
+0x0d 0xc0 0x35 0x62
+# CHECK: cs1 = r21
+0x11 0xc0 0x0d 0x6a
+# CHECK: r17 = cs1