-; RUN: llc < %s -mtriple=x86_64-darwin -x86-experimental-vector-widening-legalization -mattr=+mmx,+sse2 | FileCheck %s
+; RUN: llc < %s -march=x86_64 -mattr=+mmx,+sse2 | FileCheck %s
define i32 @test0(<1 x i64>* %v4) {
; CHECK-LABEL: test0:
-; CHECK: ## BB#0:
-; CHECK-NEXT: pshufw $238, (%rdi), %mm0
+; CHECK: # BB#0:{{.*}} %entry
+; CHECK: pshufw $238, (%[[REG:[a-z]+]]), %mm0
; CHECK-NEXT: movd %mm0, %eax
; CHECK-NEXT: addl $32, %eax
; CHECK-NEXT: retq
+entry:
%v5 = load <1 x i64>* %v4, align 8
%v12 = bitcast <1 x i64> %v5 to <4 x i16>
%v13 = bitcast <4 x i16> %v12 to x86_mmx
define i32 @test1(i32* nocapture readonly %ptr) {
; CHECK-LABEL: test1:
-; CHECK: ## BB#0: ## %entry
-; CHECK-NEXT: movd (%rdi), %mm0
+; CHECK: # BB#0:{{.*}} %entry
+; CHECK: movd (%[[REG]]), %mm0
; CHECK-NEXT: pshufw $232, %mm0, %mm0
; CHECK-NEXT: movd %mm0, %eax
; CHECK-NEXT: emms
define i32 @test2(i32* nocapture readonly %ptr) {
; CHECK-LABEL: test2:
-; CHECK: ## BB#0: ## %entry
-; CHECK-NEXT: pshufw $232, (%rdi), %mm0
+; CHECK: # BB#0:{{.*}} %entry
+; CHECK: pshufw $232, (%[[REG]]), %mm0
; CHECK-NEXT: movd %mm0, %eax
; CHECK-NEXT: emms
; CHECK-NEXT: retq