-; RUN: llc -march=x86 %s -o -
-; RUN: llc -march=x86-64 %s -o -
-
+; REQUIRES: asserts
+; RUN: llc -march=x86 -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness
+; RUN: llc -march=x86-64 -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness
+
; PR6497
; Chain and flag folding issues.
define i32 @test1() nounwind ssp {
entry:
- %tmp5.i = volatile load i32* undef ; <i32> [#uses=1]
+ %tmp5.i = load volatile i32, i32* undef ; <i32> [#uses=1]
%conv.i = zext i32 %tmp5.i to i64 ; <i64> [#uses=1]
- %tmp12.i = volatile load i32* undef ; <i32> [#uses=1]
+ %tmp12.i = load volatile i32, i32* undef ; <i32> [#uses=1]
%conv13.i = zext i32 %tmp12.i to i64 ; <i64> [#uses=1]
%shl.i = shl i64 %conv13.i, 32 ; <i64> [#uses=1]
%or.i = or i64 %shl.i, %conv.i ; <i64> [#uses=1]
%add16.i = add i64 %or.i, 256 ; <i64> [#uses=1]
%shr.i = lshr i64 %add16.i, 8 ; <i64> [#uses=1]
%conv19.i = trunc i64 %shr.i to i32 ; <i32> [#uses=1]
- volatile store i32 %conv19.i, i32* undef
+ store volatile i32 %conv19.i, i32* undef
ret i32 undef
}
if.end: ; preds = %land.end
ret void
}
+
+; PR6577
+%pair = type { i64, double }
+
+define void @test3() {
+dependentGraph243.exit:
+ %subject19 = load %pair, %pair* undef ; <%1> [#uses=1]
+ %0 = extractvalue %pair %subject19, 1 ; <double> [#uses=2]
+ %1 = select i1 undef, double %0, double undef ; <double> [#uses=1]
+ %2 = select i1 undef, double %1, double %0 ; <double> [#uses=1]
+ %3 = insertvalue %pair undef, double %2, 1 ; <%1> [#uses=1]
+ store %pair %3, %pair* undef
+ ret void
+}
+
+; PR6605
+define i64 @test4(i8* %P) nounwind ssp {
+entry:
+ %tmp1 = load i8, i8* %P ; <i8> [#uses=3]
+ %tobool = icmp eq i8 %tmp1, 0 ; <i1> [#uses=1]
+ %tmp58 = sext i1 %tobool to i8 ; <i8> [#uses=1]
+ %mul.i = and i8 %tmp58, %tmp1 ; <i8> [#uses=1]
+ %conv6 = zext i8 %mul.i to i32 ; <i32> [#uses=1]
+ %cmp = icmp ne i8 %tmp1, 1 ; <i1> [#uses=1]
+ %conv11 = zext i1 %cmp to i32 ; <i32> [#uses=1]
+ %call12 = tail call i32 @safe(i32 %conv11) nounwind ; <i32> [#uses=1]
+ %and = and i32 %conv6, %call12 ; <i32> [#uses=1]
+ %tobool13 = icmp eq i32 %and, 0 ; <i1> [#uses=1]
+ br i1 %tobool13, label %if.else, label %return
+
+if.else: ; preds = %entry
+ br label %return
+
+return: ; preds = %if.else, %entry
+ ret i64 undef
+}
+
+declare i32 @safe(i32)
+
+; PR6607
+define fastcc void @test5(i32 %FUNC) nounwind {
+foo:
+ %0 = load i8, i8* undef, align 1 ; <i8> [#uses=3]
+ %1 = sext i8 %0 to i32 ; <i32> [#uses=2]
+ %2 = zext i8 %0 to i32 ; <i32> [#uses=1]
+ %tmp1.i5037 = urem i32 %2, 10 ; <i32> [#uses=1]
+ %tmp.i5038 = icmp ugt i32 %tmp1.i5037, 15 ; <i1> [#uses=1]
+ %3 = zext i1 %tmp.i5038 to i8 ; <i8> [#uses=1]
+ %4 = icmp slt i8 %0, %3 ; <i1> [#uses=1]
+ %5 = add nsw i32 %1, 256 ; <i32> [#uses=1]
+ %storemerge.i.i57 = select i1 %4, i32 %5, i32 %1 ; <i32> [#uses=1]
+ %6 = shl i32 %storemerge.i.i57, 16 ; <i32> [#uses=1]
+ %7 = sdiv i32 %6, -256 ; <i32> [#uses=1]
+ %8 = trunc i32 %7 to i8 ; <i8> [#uses=1]
+ store i8 %8, i8* undef, align 1
+ ret void
+}
+
+
+; Crash commoning identical asms.
+; PR6803
+define void @test6(i1 %C) nounwind optsize ssp {
+entry:
+ br i1 %C, label %do.body55, label %do.body92
+
+do.body55: ; preds = %if.else36
+ call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !0
+ ret void
+
+do.body92: ; preds = %if.then66
+ call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !1
+ ret void
+}
+
+!0 = !{i32 633550}
+!1 = !{i32 634261}
+
+
+; Crash during XOR optimization.
+; <rdar://problem/7869290>
+
+define void @test7() nounwind ssp {
+entry:
+ br i1 undef, label %bb14, label %bb67
+
+bb14:
+ %tmp0 = trunc i16 undef to i1
+ %tmp1 = load i8, i8* undef, align 8
+ %tmp2 = shl i8 %tmp1, 4
+ %tmp3 = lshr i8 %tmp2, 7
+ %tmp4 = trunc i8 %tmp3 to i1
+ %tmp5 = icmp ne i1 %tmp0, %tmp4
+ br i1 %tmp5, label %bb14, label %bb67
+
+bb67:
+ ret void
+}
+
+; Crash when trying to copy AH to AL.
+; PR7540
+define void @copy8bitregs() nounwind {
+entry:
+ %div.i = sdiv i32 115200, 0
+ %shr8.i = lshr i32 %div.i, 8
+ %conv4.i = trunc i32 %shr8.i to i8
+ call void asm sideeffect "outb $0, ${1:w}", "{ax},N{dx},~{dirflag},~{fpsr},~{flags}"(i8 %conv4.i, i32 1017) nounwind
+ unreachable
+}
+
+; Crash trying to form conditional increment with fp value.
+; PR8981
+define i32 @test9(double %X) ssp align 2 {
+entry:
+ %0 = fcmp one double %X, 0.000000e+00
+ %cond = select i1 %0, i32 1, i32 2
+ ret i32 %cond
+}
+
+
+; PR8514 - Crash in match address do to "heroics" turning and-of-shift into
+; shift of and.
+%struct.S0 = type { i8, [2 x i8], i8 }
+
+define void @func_59(i32 %p_63) noreturn nounwind {
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.inc44, %entry
+ %p_63.addr.1 = phi i32 [ %p_63, %entry ], [ 0, %for.inc44 ]
+ %l_74.0 = phi i32 [ 0, %entry ], [ %add46, %for.inc44 ]
+ br i1 undef, label %for.inc44, label %bb.nph81
+
+bb.nph81: ; preds = %for.body
+ %tmp98 = add i32 %p_63.addr.1, 0
+ br label %for.body22
+
+for.body22: ; preds = %for.body22, %bb.nph81
+ %l_75.077 = phi i64 [ %ins, %for.body22 ], [ undef, %bb.nph81 ]
+ %tmp110 = trunc i64 %l_75.077 to i32
+ %tmp111 = and i32 %tmp110, 65535
+ %arrayidx32.0 = getelementptr [9 x [5 x [2 x %struct.S0]]], [9 x [5 x [2 x %struct.S0]]]* undef, i32 0, i32 %l_74.0, i32 %tmp98, i32 %tmp111, i32 0
+ store i8 1, i8* %arrayidx32.0, align 4
+ %tmp106 = shl i32 %tmp110, 2
+ %tmp107 = and i32 %tmp106, 262140
+ %scevgep99.sum114 = or i32 %tmp107, 1
+ %arrayidx32.1.1 = getelementptr [9 x [5 x [2 x %struct.S0]]], [9 x [5 x [2 x %struct.S0]]]* undef, i32 0, i32 %l_74.0, i32 %tmp98, i32 0, i32 1, i32 %scevgep99.sum114
+ store i8 0, i8* %arrayidx32.1.1, align 1
+ %ins = or i64 undef, undef
+ br label %for.body22
+
+for.inc44: ; preds = %for.body
+ %add46 = add i32 %l_74.0, 1
+ br label %for.body
+}
+
+; PR9028
+define void @func_60(i64 %A) nounwind {
+entry:
+ %0 = zext i64 %A to i160
+ %1 = shl i160 %0, 64
+ %2 = zext i160 %1 to i576
+ %3 = zext i96 undef to i576
+ %4 = or i576 %3, %2
+ store i576 %4, i576* undef, align 8
+ ret void
+}
+
+; <rdar://problem/9187792>
+define fastcc void @func_61() nounwind sspreq {
+entry:
+ %t1 = tail call i64 @llvm.objectsize.i64.p0i8(i8* undef, i1 false)
+ %t2 = icmp eq i64 %t1, -1
+ br i1 %t2, label %bb2, label %bb1
+
+bb1:
+ ret void
+
+bb2:
+ ret void
+}
+
+declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) nounwind readnone
+
+; PR10277
+; This test has dead code elimination caused by remat during spilling.
+; DCE causes a live interval to break into connected components.
+; One of the components is spilled.
+
+%t2 = type { i8 }
+%t9 = type { %t10 }
+%t10 = type { %t11 }
+%t11 = type { %t12 }
+%t12 = type { %t13*, %t13*, %t13* }
+%t13 = type { %t14*, %t15, %t15 }
+%t14 = type opaque
+%t15 = type { i8, i32, i32 }
+%t16 = type { %t17, i8* }
+%t17 = type { %t18 }
+%t18 = type { %t19 }
+%t19 = type { %t20*, %t20*, %t20* }
+%t20 = type { i32, i32 }
+%t21 = type { %t13* }
+
+define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE() ssp align 2 {
+bb:
+ %tmp = load %t9*, %t9** undef, align 4
+ %tmp2 = getelementptr inbounds %t9, %t9* %tmp, i32 0, i32 0
+ %tmp3 = getelementptr inbounds %t9, %t9* %tmp, i32 0, i32 0, i32 0, i32 0, i32 1
+ br label %bb4
+
+bb4: ; preds = %bb37, %bb
+ %tmp5 = phi i96 [ undef, %bb ], [ %tmp38, %bb37 ]
+ %tmp6 = phi i96 [ undef, %bb ], [ %tmp39, %bb37 ]
+ br i1 undef, label %bb34, label %bb7
+
+bb7: ; preds = %bb4
+ %tmp8 = load i32, i32* undef, align 4
+ %tmp9 = and i96 %tmp6, 4294967040
+ %tmp10 = zext i32 %tmp8 to i96
+ %tmp11 = shl nuw nsw i96 %tmp10, 32
+ %tmp12 = or i96 %tmp9, %tmp11
+ %tmp13 = or i96 %tmp12, 1
+ %tmp14 = load i32, i32* undef, align 4
+ %tmp15 = and i96 %tmp5, 4294967040
+ %tmp16 = zext i32 %tmp14 to i96
+ %tmp17 = shl nuw nsw i96 %tmp16, 32
+ %tmp18 = or i96 %tmp15, %tmp17
+ %tmp19 = or i96 %tmp18, 1
+ %tmp20 = load i8, i8* undef, align 1
+ %tmp21 = and i8 %tmp20, 1
+ %tmp22 = icmp ne i8 %tmp21, 0
+ %tmp23 = select i1 %tmp22, i96 %tmp19, i96 %tmp13
+ %tmp24 = select i1 %tmp22, i96 %tmp13, i96 %tmp19
+ store i96 %tmp24, i96* undef, align 4
+ %tmp25 = load %t13*, %t13** %tmp3, align 4
+ %tmp26 = icmp eq %t13* %tmp25, undef
+ br i1 %tmp26, label %bb28, label %bb27
+
+bb27: ; preds = %bb7
+ br label %bb29
+
+bb28: ; preds = %bb7
+ call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef)
+ br label %bb29
+
+bb29: ; preds = %bb28, %bb27
+ store i96 %tmp23, i96* undef, align 4
+ %tmp30 = load %t13*, %t13** %tmp3, align 4
+ br i1 false, label %bb33, label %bb31
+
+bb31: ; preds = %bb29
+ %tmp32 = getelementptr inbounds %t13, %t13* %tmp30, i32 1
+ store %t13* %tmp32, %t13** %tmp3, align 4
+ br label %bb37
+
+bb33: ; preds = %bb29
+ unreachable
+
+bb34: ; preds = %bb4
+ br i1 undef, label %bb36, label %bb35
+
+bb35: ; preds = %bb34
+ store %t13* null, %t13** %tmp3, align 4
+ br label %bb37
+
+bb36: ; preds = %bb34
+ call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef)
+ br label %bb37
+
+bb37: ; preds = %bb36, %bb35, %bb31
+ %tmp38 = phi i96 [ %tmp23, %bb31 ], [ %tmp5, %bb35 ], [ %tmp5, %bb36 ]
+ %tmp39 = phi i96 [ %tmp24, %bb31 ], [ %tmp6, %bb35 ], [ %tmp6, %bb36 ]
+ %tmp40 = add i32 undef, 1
+ br label %bb4
+}
+
+declare %t14* @_ZN4llvm9MCContext16CreateTempSymbolEv(%t2*)
+
+declare void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10*, %t21* byval align 4, %t13*)
+
+declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
+
+declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind
+
+; PR10463
+; Spilling a virtual register with <undef> uses.
+define void @autogen_239_1000() {
+BB:
+ %Shuff = shufflevector <8 x double> undef, <8 x double> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 undef, i32 undef>
+ br label %CF
+
+CF:
+ %B16 = frem <8 x double> zeroinitializer, %Shuff
+ %E19 = extractelement <8 x double> %Shuff, i32 5
+ br i1 undef, label %CF, label %CF75
+
+CF75:
+ br i1 undef, label %CF75, label %CF76
+
+CF76:
+ store double %E19, double* undef
+ br i1 undef, label %CF76, label %CF77
+
+CF77:
+ %B55 = fmul <8 x double> %B16, undef
+ br label %CF77
+}
+
+; PR10527
+define void @pr10527() nounwind uwtable {
+entry:
+ br label %"4"
+
+"3":
+ %0 = load <2 x i32>, <2 x i32>* null, align 8
+ %1 = xor <2 x i32> zeroinitializer, %0
+ %2 = and <2 x i32> %1, %6
+ %3 = or <2 x i32> undef, %2
+ %4 = and <2 x i32> %3, undef
+ store <2 x i32> %4, <2 x i32>* undef
+ %5 = load <2 x i32>, <2 x i32>* undef, align 1
+ br label %"4"
+
+"4":
+ %6 = phi <2 x i32> [ %5, %"3" ], [ zeroinitializer, %entry ]
+ %7 = icmp ult i32 undef, undef
+ br i1 %7, label %"3", label %"5"
+
+"5":
+ ret void
+}
+
+; PR11078
+;
+; A virtual register used by the "foo" inline asm memory operand gets
+; constrained to GR32_ABCD during coalescing. This makes the inline asm
+; impossible to allocate without splitting the live range and reinflating the
+; register class around the inline asm.
+;
+; The constraint originally comes from the TEST8ri optimization of (icmp (and %t0, 1), 0).
+
+@__force_order = external hidden global i32, align 4
+define void @pr11078(i32* %pgd) nounwind {
+entry:
+ %t0 = load i32, i32* %pgd, align 4
+ %and2 = and i32 %t0, 1
+ %tobool = icmp eq i32 %and2, 0
+ br i1 %tobool, label %if.then, label %if.end
+
+if.then:
+ %t1 = tail call i32 asm sideeffect "bar", "=r,=*m,~{dirflag},~{fpsr},~{flags}"(i32* @__force_order) nounwind
+ br label %if.end
+
+if.end:
+ %t6 = inttoptr i32 %t0 to i64*
+ %t11 = tail call i64 asm sideeffect "foo", "=*m,=A,{bx},{cx},1,~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %t6, i32 0, i32 0, i64 0) nounwind
+ ret void
+}
+
+; Avoid emitting wrong kill flags from InstrEmitter.
+; InstrEmitter::EmitSubregNode() may steal virtual registers from already
+; emitted blocks when isCoalescableExtInstr points out the opportunity.
+; Make sure kill flags are cleared on the newly global virtual register.
+define i64 @ov_read(i8* %vf, i8* nocapture %buffer, i32 %length, i32 %bigendianp, i32 %word, i32 %sgned, i32* %bitstream) nounwind uwtable ssp {
+entry:
+ br i1 undef, label %return, label %while.body.preheader
+
+while.body.preheader: ; preds = %entry
+ br i1 undef, label %if.then3, label %if.end7
+
+if.then3: ; preds = %while.body.preheader
+ %0 = load i32, i32* undef, align 4
+ br i1 undef, label %land.lhs.true.i255, label %if.end7
+
+land.lhs.true.i255: ; preds = %if.then3
+ br i1 undef, label %if.then.i256, label %if.end7
+
+if.then.i256: ; preds = %land.lhs.true.i255
+ %sub.i = sub i32 0, %0
+ %conv = sext i32 %sub.i to i64
+ br i1 undef, label %if.end7, label %while.end
+
+if.end7: ; preds = %if.then.i256, %land.lhs.true.i255, %if.then3, %while.body.preheader
+ unreachable
+
+while.end: ; preds = %if.then.i256
+ %cmp18 = icmp sgt i32 %sub.i, 0
+ %.conv = select i1 %cmp18, i64 -131, i64 %conv
+ ret i64 %.conv
+
+return: ; preds = %entry
+ ret i64 -131
+}
+
+; The tail call to a varargs function sets %AL.
+; uitofp expands to an FCMOV instruction which splits the basic block.
+; Make sure the live range of %AL isn't split.
+@.str = private unnamed_addr constant { [1 x i8], [63 x i8] } zeroinitializer, align 32
+define void @pr13188(i64* nocapture %this) uwtable ssp sanitize_address align 2 {
+entry:
+ %x7 = load i64, i64* %this, align 8
+ %sub = add i64 %x7, -1
+ %conv = uitofp i64 %sub to float
+ %div = fmul float %conv, 5.000000e-01
+ %conv2 = fpext float %div to double
+ tail call void (...) @_Z6PrintFz(i8* getelementptr inbounds ({ [1 x i8], [63 x i8] }, { [1 x i8], [63 x i8] }* @.str, i64 0, i32 0, i64 0), double %conv2)
+ ret void
+}
+declare void @_Z6PrintFz(...)
+
+@a = external global i32, align 4
+@fn1.g = private unnamed_addr constant [9 x i32*] [i32* null, i32* @a, i32* null, i32* null, i32* null, i32* null, i32* null, i32* null, i32* null], align 16
+@e = external global i32, align 4
+
+define void @pr13943() nounwind uwtable ssp {
+entry:
+ %srcval = load i576, i576* bitcast ([9 x i32*]* @fn1.g to i576*), align 16
+ br label %for.cond
+
+for.cond: ; preds = %for.inc, %entry
+ %g.0 = phi i576 [ %srcval, %entry ], [ %ins, %for.inc ]
+ %0 = load i32, i32* @e, align 4
+ %1 = lshr i576 %g.0, 64
+ %2 = trunc i576 %1 to i64
+ %3 = inttoptr i64 %2 to i32*
+ %cmp = icmp eq i32* undef, %3
+ %conv2 = zext i1 %cmp to i32
+ %and = and i32 %conv2, %0
+ tail call void (...) @fn3(i32 %and) nounwind
+ %tobool = icmp eq i32 undef, 0
+ br i1 %tobool, label %for.inc, label %if.then
+
+if.then: ; preds = %for.cond
+ ret void
+
+for.inc: ; preds = %for.cond
+ %4 = shl i576 %1, 384
+ %mask = and i576 %g.0, -726838724295606890509921801691610055141362320587174446476410459910173841445449629921945328942266354949348255351381262292727973638307841
+ %5 = and i576 %4, 726838724295606890509921801691610055141362320587174446476410459910173841445449629921945328942266354949348255351381262292727973638307840
+ %ins = or i576 %5, %mask
+ br label %for.cond
+}
+
+declare void @fn3(...)
+
+; Check coalescing of IMPLICIT_DEF instructions:
+;
+; %vreg1 = IMPLICIT_DEF
+; %vreg2 = MOV32r0
+;
+; When coalescing %vreg1 and %vreg2, the IMPLICIT_DEF instruction should be
+; erased along with its value number.
+;
+define void @rdar12474033() nounwind ssp {
+bb:
+ br i1 undef, label %bb21, label %bb1
+
+bb1: ; preds = %bb
+ switch i32 undef, label %bb10 [
+ i32 4, label %bb2
+ i32 1, label %bb9
+ i32 5, label %bb3
+ i32 6, label %bb3
+ i32 2, label %bb9
+ ]
+
+bb2: ; preds = %bb1
+ unreachable
+
+bb3: ; preds = %bb1, %bb1
+ br i1 undef, label %bb4, label %bb5
+
+bb4: ; preds = %bb3
+ unreachable
+
+bb5: ; preds = %bb3
+ %tmp = load <4 x float>, <4 x float>* undef, align 1
+ %tmp6 = bitcast <4 x float> %tmp to i128
+ %tmp7 = load <4 x float>, <4 x float>* undef, align 1
+ %tmp8 = bitcast <4 x float> %tmp7 to i128
+ br label %bb10
+
+bb9: ; preds = %bb1, %bb1
+ unreachable
+
+bb10: ; preds = %bb5, %bb1
+ %tmp11 = phi i128 [ undef, %bb1 ], [ %tmp6, %bb5 ]
+ %tmp12 = phi i128 [ 0, %bb1 ], [ %tmp8, %bb5 ]
+ switch i32 undef, label %bb21 [
+ i32 2, label %bb18
+ i32 3, label %bb13
+ i32 5, label %bb16
+ i32 6, label %bb17
+ i32 1, label %bb18
+ ]
+
+bb13: ; preds = %bb10
+ br i1 undef, label %bb15, label %bb14
+
+bb14: ; preds = %bb13
+ br label %bb21
+
+bb15: ; preds = %bb13
+ unreachable
+
+bb16: ; preds = %bb10
+ unreachable
+
+bb17: ; preds = %bb10
+ unreachable
+
+bb18: ; preds = %bb10, %bb10
+ %tmp19 = bitcast i128 %tmp11 to <4 x float>
+ %tmp20 = bitcast i128 %tmp12 to <4 x float>
+ br label %bb21
+
+bb21: ; preds = %bb18, %bb14, %bb10, %bb
+ %tmp22 = phi <4 x float> [ undef, %bb ], [ undef, %bb10 ], [ undef, %bb14 ], [ %tmp20, %bb18 ]
+ %tmp23 = phi <4 x float> [ undef, %bb ], [ undef, %bb10 ], [ undef, %bb14 ], [ %tmp19, %bb18 ]
+ store <4 x float> %tmp23, <4 x float>* undef, align 16
+ store <4 x float> %tmp22, <4 x float>* undef, align 16
+ switch i32 undef, label %bb29 [
+ i32 5, label %bb27
+ i32 1, label %bb24
+ i32 2, label %bb25
+ i32 14, label %bb28
+ i32 4, label %bb26
+ ]
+
+bb24: ; preds = %bb21
+ unreachable
+
+bb25: ; preds = %bb21
+ br label %bb29
+
+bb26: ; preds = %bb21
+ br label %bb29
+
+bb27: ; preds = %bb21
+ unreachable
+
+bb28: ; preds = %bb21
+ br label %bb29
+
+bb29: ; preds = %bb28, %bb26, %bb25, %bb21
+ unreachable
+}
+
+define void @pr14194() nounwind uwtable {
+ %tmp = load i64, i64* undef, align 16
+ %tmp1 = trunc i64 %tmp to i32
+ %tmp2 = lshr i64 %tmp, 32
+ %tmp3 = trunc i64 %tmp2 to i32
+ %tmp4 = call { i32, i32 } asm sideeffect "", "=&r,=&r,r,r,0,1,~{dirflag},~{fpsr},~{flags}"(i32 %tmp3, i32 undef, i32 %tmp3, i32 %tmp1) nounwind
+ ret void
+}
projects / oota-llvm.git / blobdiff