declare i32 @llvm.x86.bmi.bextr.32(i32, i32) nounwind readnone
+define i32 @bextr32b(i32 %x) nounwind uwtable readnone ssp {
+ %1 = lshr i32 %x, 4
+ %2 = and i32 %1, 4095
+ ret i32 %2
+; CHECK-LABEL: bextr32b:
+; CHECK: bextrl
+}
+
+define i32 @bextr32b_load(i32* %x) nounwind uwtable readnone ssp {
+ %1 = load i32* %x
+ %2 = lshr i32 %1, 4
+ %3 = and i32 %2, 4095
+ ret i32 %3
+; CHECK-LABEL: bextr32b_load:
+; CHECK: bextrl {{.*}}, ({{.*}}), {{.*}}
+}
+
define i64 @bextr64(i64 %x, i64 %y) nounwind readnone {
%tmp = tail call i64 @llvm.x86.bmi.bextr.64(i64 %x, i64 %y)
ret i64 %tmp
declare i64 @llvm.x86.bmi.bextr.64(i64, i64) nounwind readnone
+define i64 @bextr64b(i64 %x) nounwind uwtable readnone ssp {
+ %1 = lshr i64 %x, 4
+ %2 = and i64 %1, 4095
+ ret i64 %2
+; CHECK-LABEL: bextr64b:
+; CHECK: bextrq
+}
+
define i32 @bzhi32(i32 %x, i32 %y) nounwind readnone {
%tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x, i32 %y)
ret i32 %tmp
; CHECK: bzhiq
}
+define i64 @bzhi64_constant_mask(i64 %x) #0 {
+entry:
+ %and = and i64 %x, 4611686018427387903
+ ret i64 %and
+; CHECK-LABEL: bzhi64_constant_mask:
+; CHECK: movb $62, %al
+; CHECK: bzhiq %rax, %r[[ARG1:di|cx]], %rax
+}
+
+define i64 @bzhi64_small_constant_mask(i64 %x) #0 {
+entry:
+ %and = and i64 %x, 2147483647
+ ret i64 %and
+; CHECK-LABEL: bzhi64_small_constant_mask:
+; CHECK: andq $2147483647, %r[[ARG1]]
+}
+
define i32 @blsi32(i32 %x) nounwind readnone {
%tmp = sub i32 0, %x
%tmp2 = and i32 %x, %tmp