[FastISel][AArch64] Use 'cbz' also for null values (pointers).

[oota-llvm.git] / test / CodeGen / X86 / atomic-load-store-wide.ll

diff --git a/test/CodeGen/X86/atomic-load-store-wide.ll b/test/CodeGen/X86/atomic-load-store-wide.ll
index 227883e55926b2fca2d6e18bdbf15ac61f378047..ad1a5c6d02679b5ffb8c84a0fe2a1954b8e83ea0 100644 (file)
--- a/test/CodeGen/X86/atomic-load-store-wide.ll
+++ b/test/CodeGen/X86/atomic-load-store-wide.ll
@@ -1,19 +1,21 @@
-; RUN: llc < %s -march=x86 | FileCheck %s
+; RUN: llc < %s -mcpu=corei7 -march=x86 -verify-machineinstrs | FileCheck %s
 
 ; 64-bit load/store on x86-32
 ; FIXME: The generated code can be substantially improved.
 
 define void @test1(i64* %ptr, i64 %val1) {
-; CHECK: test1
-; CHECK: cmpxchg8b
+; CHECK-LABEL: test1
+; CHECK: lock
+; CHECK-NEXT: cmpxchg8b
 ; CHECK-NEXT: jne
-  store atomic i64 %val1, i64* %ptr seq_cst, align 4
+  store atomic i64 %val1, i64* %ptr seq_cst, align 8
   ret void
 }
 
 define i64 @test2(i64* %ptr) {
-; CHECK: test2
-; CHECK: cmpxchg8b
-  %val = load atomic i64* %ptr seq_cst, align 4
+; CHECK-LABEL: test2
+; CHECK: lock
+; CHECK-NEXT: cmpxchg8b
+  %val = load atomic i64* %ptr seq_cst, align 8
   ret i64 %val
 }