[AVX512] add PSLLD and PSLLQ Intrinsic

[oota-llvm.git] / test / CodeGen / X86 / TruncAssertZext.ll

diff --git a/test/CodeGen/X86/TruncAssertZext.ll b/test/CodeGen/X86/TruncAssertZext.ll
index 2d78b5fadc20db8cff8dc216a8bf342229a6ecaa..8c664127f92abaa5f627ad527232a21448810144 100644 (file)
--- a/test/CodeGen/X86/TruncAssertZext.ll
+++ b/test/CodeGen/X86/TruncAssertZext.ll
@@ -1,16 +1,16 @@
-; RUN: llc < %s -O2 -march=x86-64 | FileCheck %s\r
-; Checks that a zeroing mov is inserted for the trunc/zext pair even when\r
-; the source of the zext is an AssertSext node\r
-; PR20494\r
-\r
-define i64 @main(i64 %a) { \r
-; CHECK-LABEL: main\r
-; CHECK: movl %e{{..}}, %eax\r
-; CHECK: ret\r
-  %or = or i64 %a, -2\r
-  %trunc = trunc i64 %or to i32\r
-  br label %l\r
-l:\r
-  %ext = zext i32 %trunc to i64\r
-  ret i64 %ext\r
-}\r
+; RUN: llc < %s -O2 -march=x86-64 | FileCheck %s
+; Checks that a zeroing mov is inserted for the trunc/zext pair even when
+; the source of the zext is an AssertSext node
+; PR20494
+
+define i64 @main(i64 %a) {
+; CHECK-LABEL: main
+; CHECK: movl %e{{..}}, %eax
+; CHECK: ret
+  %or = or i64 %a, -2
+  %trunc = trunc i64 %or to i32
+  br label %l
+l:
+  %ext = zext i32 %trunc to i64
+  ret i64 %ext
+}