llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll: s/REQUIRE/REQUIRES/

[oota-llvm.git] / test / CodeGen / Thumb2 / thumb2-ror.ll

diff --git a/test/CodeGen/Thumb2/thumb2-ror.ll b/test/CodeGen/Thumb2/thumb2-ror.ll
index c44fdb3ad507e71b4914355367c4518c78f4f00c..71b00153c2985c39c596a8d08c7159d76318d69d 100644 (file)
--- a/test/CodeGen/Thumb2/thumb2-ror.ll
+++ b/test/CodeGen/Thumb2/thumb2-ror.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=THUMB1
 
-
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK:       ror.w   r0, r0, #22
 define i32 @f1(i32 %a) {
     %l8 = shl i32 %a, 10
@@ -10,13 +10,17 @@ define i32 @f1(i32 %a) {
     ret i32 %tmp
 }
 
-; CHECK: f2:
+; CHECK-LABEL: f2:
+; CHECK-NOT: and
 ; CHECK: ror
+; THUMB1: f2
+; THUMB1: and
 define i32 @f2(i32 %v, i32 %nbits) {
 entry:
-  %shr = lshr i32 %v, %nbits
-  %sub = sub i32 32, %nbits
+  %and = and i32 %nbits, 31
+  %shr = lshr i32 %v, %and
+  %sub = sub i32 32, %and
   %shl = shl i32 %v, %sub
   %or = or i32 %shl, %shr
   ret i32 %or
-}
\ No newline at end of file
+}