ARM: yet another round of ARM test clean ups

[oota-llvm.git] / test / CodeGen / Thumb2 / thumb2-and.ll

diff --git a/test/CodeGen/Thumb2/thumb2-and.ll b/test/CodeGen/Thumb2/thumb2-and.ll
index ea5b096f3b9243771d9a79955633546a0d983182..1984b3ffb356ba1ef8239cb557135db0c91944d0 100644 (file)
--- a/test/CodeGen/Thumb2/thumb2-and.ll
+++ b/test/CodeGen/Thumb2/thumb2-and.ll
@@ -1,14 +1,14 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ands r0, r1
     %tmp = and i32 %a, %b
     ret i32 %tmp
 }
 
 define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: and.w r0, r0, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = and i32 %a, %tmp
@@ -16,7 +16,7 @@ define i32 @f2(i32 %a, i32 %b) {
 }
 
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: and.w r0, r0, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = and i32 %a, %tmp
@@ -24,7 +24,7 @@ define i32 @f3(i32 %a, i32 %b) {
 }
 
 define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: and.w r0, r0, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = and i32 %a, %tmp
@@ -32,7 +32,7 @@ define i32 @f4(i32 %a, i32 %b) {
 }
 
 define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: and.w r0, r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8