Fix typo.

[oota-llvm.git] / test / CodeGen / PowerPC / vec_perf_shuffle.ll

diff --git a/test/CodeGen/PowerPC/vec_perf_shuffle.ll b/test/CodeGen/PowerPC/vec_perf_shuffle.ll
index 6177b5f4c68a74f11224b9f6b391200741de3aae..f8b37fae7c23d5bfd55c4cddba5f9e96e3620f5f 100644 (file)
--- a/test/CodeGen/PowerPC/vec_perf_shuffle.ll
+++ b/test/CodeGen/PowerPC/vec_perf_shuffle.ll
@@ -1,42 +1,36 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep vperm
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep vperm
 
-<4 x float> %test_uu72(<4 x float> *%P1, <4 x float> *%P2) {
-       %V1 = load <4 x float> *%P1
-       %V2 = load <4 x float> *%P2
-       ; vmrglw + vsldoi
-       %V3 = shufflevector <4 x float> %V1, <4 x float> %V2,
-                           <4 x uint> <uint undef, uint undef, uint 7, uint 2>
+define <4 x float> @test_uu72(<4 x float>* %P1, <4 x float>* %P2) {
+       %V1 = load <4 x float>, <4 x float>* %P1                ; <<4 x float>> [#uses=1]
+       %V2 = load <4 x float>, <4 x float>* %P2                ; <<4 x float>> [#uses=1]
+       %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 undef, i32 undef, i32 7, i32 2 >          ; <<4 x float>> [#uses=1]
        ret <4 x float> %V3
 }
 
-<4 x float> %test_30u5(<4 x float> *%P1, <4 x float> *%P2) {
-       %V1 = load <4 x float> *%P1
-       %V2 = load <4 x float> *%P2
-       %V3 = shufflevector <4 x float> %V1, <4 x float> %V2,
-                 <4 x uint> <uint 3, uint 0, uint undef, uint 5>
+define <4 x float> @test_30u5(<4 x float>* %P1, <4 x float>* %P2) {
+       %V1 = load <4 x float>, <4 x float>* %P1                ; <<4 x float>> [#uses=1]
+       %V2 = load <4 x float>, <4 x float>* %P2                ; <<4 x float>> [#uses=1]
+       %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 0, i32 undef, i32 5 >              ; <<4 x float>> [#uses=1]
        ret <4 x float> %V3
 }
 
-<4 x float> %test_3u73(<4 x float> *%P1, <4 x float> *%P2) {
-       %V1 = load <4 x float> *%P1
-       %V2 = load <4 x float> *%P2
-       %V3 = shufflevector <4 x float> %V1, <4 x float> %V2,
-                 <4 x uint> <uint 3, uint undef, uint 7, uint 3>
+define <4 x float> @test_3u73(<4 x float>* %P1, <4 x float>* %P2) {
+       %V1 = load <4 x float>, <4 x float>* %P1                ; <<4 x float>> [#uses=1]
+       %V2 = load <4 x float>, <4 x float>* %P2                ; <<4 x float>> [#uses=1]
+       %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 undef, i32 7, i32 3 >              ; <<4 x float>> [#uses=1]
        ret <4 x float> %V3
 }
 
-<4 x float> %test_3774(<4 x float> *%P1, <4 x float> *%P2) {
-       %V1 = load <4 x float> *%P1
-       %V2 = load <4 x float> *%P2
-       %V3 = shufflevector <4 x float> %V1, <4 x float> %V2,
-                 <4 x uint> <uint 3, uint 7, uint 7, uint 4>
+define <4 x float> @test_3774(<4 x float>* %P1, <4 x float>* %P2) {
+       %V1 = load <4 x float>, <4 x float>* %P1                ; <<4 x float>> [#uses=1]
+       %V2 = load <4 x float>, <4 x float>* %P2                ; <<4 x float>> [#uses=1]
+       %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 7, i32 7, i32 4 >          ; <<4 x float>> [#uses=1]
        ret <4 x float> %V3
 }
 
-<4 x float> %test_4450(<4 x float> *%P1, <4 x float> *%P2) {
-       %V1 = load <4 x float> *%P1
-       %V2 = load <4 x float> *%P2
-       %V3 = shufflevector <4 x float> %V1, <4 x float> %V2,
-                 <4 x uint> <uint 4, uint 4, uint 5, uint 0>
+define <4 x float> @test_4450(<4 x float>* %P1, <4 x float>* %P2) {
+       %V1 = load <4 x float>, <4 x float>* %P1                ; <<4 x float>> [#uses=1]
+       %V2 = load <4 x float>, <4 x float>* %P2                ; <<4 x float>> [#uses=1]
+       %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 4, i32 4, i32 5, i32 0 >          ; <<4 x float>> [#uses=1]
        ret <4 x float> %V3
 }