llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll: s/REQUIRE/REQUIRES/

[oota-llvm.git] / test / CodeGen / PowerPC / rlwimi-and.ll

diff --git a/test/CodeGen/PowerPC/rlwimi-and.ll b/test/CodeGen/PowerPC/rlwimi-and.ll
index 213363ee819ff73f349ec35bdb9cfebde0e4a13f..59f704ee16bc342480e749493bf78b0e0fdcc677 100644 (file)
--- a/test/CodeGen/PowerPC/rlwimi-and.ll
+++ b/test/CodeGen/PowerPC/rlwimi-and.ll
@@ -16,11 +16,11 @@ codeRepl12:                                       ; preds = %codeRepl4
   unreachable
 
 codeRepl17:                                       ; preds = %codeRepl4
-  %0 = load i8* undef, align 2
+  %0 = load i8, i8* undef, align 2
   %1 = and i8 %0, 1
   %not.tobool.i.i.i = icmp eq i8 %1, 0
   %2 = select i1 %not.tobool.i.i.i, i16 0, i16 256
-  %3 = load i8* undef, align 1
+  %3 = load i8, i8* undef, align 1
   %4 = and i8 %3, 1
   %not.tobool.i.1.i.i = icmp eq i8 %4, 0
   %rvml38.sroa.1.1.insert.ext = select i1 %not.tobool.i.1.i.i, i16 0, i16 1
@@ -28,11 +28,9 @@ codeRepl17:                                       ; preds = %codeRepl4
   store i16 %rvml38.sroa.0.0.insert.insert, i16* undef, align 2
   unreachable
 
-; FIXME: the SLWI could be folded into the RLWIMI to give a rotate of 8.
 ; CHECK: @test
-; CHECK-DAG: slwi [[R1:[0-9]+]], {{[0-9]+}}, 31
-; CHECK-DAG: rlwinm [[R2:[0-9]+]], {{[0-9]+}}, 0, 31, 31
-; CHECK: rlwimi [[R2]], [[R1]], 9, 23, 23
+; CHECK: clrlwi [[R1:[0-9]+]], {{[0-9]+}}, 31
+; CHECK: rlwimi [[R1]], {{[0-9]+}}, 8, 23, 23
 
 codeRepl29:                                       ; preds = %codeRepl1
   unreachable