; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
@v2f64 = global <2 x double> <double 0.0, double 0.0>
; MIPS32: fill.w [[R2:\$w[0-9]+]], [[R1]]
store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
- ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
+ ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+ ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
; MIPS32: lui [[R1:\$[0-9]+]], 18304
; MIPS32: fill.w [[R3:\$w[0-9]+]], [[R2]]
store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
- ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
+ ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+ ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
- ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
+ ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+ ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void
; MIPS32: .size const_v4f32
; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
- ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
+ ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+ ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
- ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
+ ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+ ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
- ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
+ ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+ ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
- ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
+ ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+ ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
- ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
+ ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+ ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
- ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
+ ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+ ; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void
; MIPS32: .size const_v2f64
; MIPS32: .size extract_v4f32_elt0
}
+define float @extract_v4f32_elt2() nounwind {
+ ; MIPS32: extract_v4f32_elt2:
+
+ %1 = load <4 x float>* @v4f32
+ ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
+
+ %2 = fadd <4 x float> %1, %1
+ ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+
+ %3 = extractelement <4 x float> %2, i32 2
+ ; Element 2 can be obtained by splatting it across the vector and extracting
+ ; $w0:sub_lo
+ ; MIPS32-DAG: splati.w $w0, [[R1]][2]
+
+ ret float %3
+ ; MIPS32: .size extract_v4f32_elt2
+}
+
define double @extract_v2f64() nounwind {
; MIPS32: extract_v2f64: