- ; 32R1-R2: sllv $[[T0:[0-9]+]], $4, $7
- ; 32R1-R2: not $[[T1:[0-9]+]], $7
- ; 32R1-R2: srl $[[T2:[0-9]+]], $5, 1
- ; 32R1-R2: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
- ; 32R1-R2: or $2, $[[T0]], $[[T3]]
- ; 32R1-R2: sllv $[[T4:[0-9]+]], $5, $7
- ; 32R1-R2: andi $[[T5:[0-9]+]], $7, 32
- ; 32R1-R2: movn $2, $[[T4]], $[[T5]]
- ; 32R1-R2: jr $ra
- ; 32R1-R2: movn $3, $zero, $[[T5]]
+ ; 32R1-R5: sllv $[[T0:[0-9]+]], $4, $7
+ ; 32R1-R5: not $[[T1:[0-9]+]], $7
+ ; 32R1-R5: srl $[[T2:[0-9]+]], $5, 1
+ ; 32R1-R5: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; 32R1-R5: or $2, $[[T0]], $[[T3]]
+ ; 32R1-R5: sllv $[[T4:[0-9]+]], $5, $7
+ ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32
+ ; 32R1-R5: movn $2, $[[T4]], $[[T5]]
+ ; 32R1-R5: jr $ra
+ ; 32R1-R5: movn $3, $zero, $[[T5]]