[mips] Optimize code generation for 64-bit variable shift instructions.

[oota-llvm.git] / test / CodeGen / Mips / llvm-ir / lshr.ll

diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll
index 7344d950cad2e6a9fcc1c04e45c8020d2fa8ab76..6fb59845f5b4884c23312f31efc76314fc745f48 100644 (file)
--- a/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -125,8 +125,7 @@ entry:
   ; 32R6:       jr        $ra
   ; 32R6:       seleqz    $2, $[[T7]], $[[T5]]
 
-  ; GP64:         sll     $[[T0:[0-9]+]], $5, 0
-  ; GP64:         dsrlv   $2, $4, $[[T0]]
+  ; GP64:         dsrlv   $2, $4, $5
 
   %r = lshr i64 %a, %b
   ret i64 %r
@@ -139,11 +138,11 @@ entry:
   ; GP32:         lw      $25, %call16(__lshrti3)($gp)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
-  ; M3:             dsrlv     $[[T1:[0-9]+]], $4, $[[T0]]
+  ; M3:             dsrlv     $[[T1:[0-9]+]], $4, $7
   ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 32
   ; M3:             bnez      $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
   ; M3:             move      $3, $[[T1]]
-  ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $[[T0]]
+  ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $7
   ; M3:             dsll      $[[T5:[0-9]+]], $4, 1
   ; M3:             not       $[[T6:[0-9]+]], $[[T0]]
   ; M3:             dsllv     $[[T7:[0-9]+]], $[[T5]], $[[T6]]
@@ -156,32 +155,32 @@ entry:
   ; M3:             jr        $ra
   ; M3:             nop
 
-  ; GP64-NOT-R6:    sll       $[[T0:[0-9]+]], $7, 0
-  ; GP64-NOT-R6:    dsrlv     $[[T1:[0-9]+]], $5, $[[T0]]
-  ; GP64-NOT-R6:    dsll      $[[T2:[0-9]+]], $4, 1
-  ; GP64-NOT-R6:    not       $[[T3:[0-9]+]], $[[T0]]
-  ; GP64-NOT-R6:    dsllv     $[[T4:[0-9]+]], $[[T2]], $[[T3]]
-  ; GP64-NOT-R6:    or        $3, $[[T4]], $[[T1]]
-  ; GP64-NOT-R6:    dsrlv     $2, $4, $[[T0]]
-  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T0]], 32
+  ; GP64-NOT-R6:    dsrlv     $[[T0:[0-9]+]], $5, $7
+  ; GP64-NOT-R6:    dsll      $[[T1:[0-9]+]], $4, 1
+  ; GP64-NOT-R6:    sll       $[[T2:[0-9]+]], $7, 0
+  ; GP64-NOT-R6:    not       $[[T3:[0-9]+]], $[[T2]]
+  ; GP64-NOT-R6:    dsllv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+  ; GP64-NOT-R6:    or        $3, $[[T4]], $[[T0]]
+  ; GP64-NOT-R6:    dsrlv     $2, $4, $7
+  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T2]], 32
   ; GP64-NOT-R6:    movn      $3, $2, $[[T5]]
   ; GP64-NOT-R6:    jr        $ra
   ; GP64-NOT-R6:    movn      $2, $zero, $1
 
-  ; 64R6:           sll       $[[T0:[0-9]+]], $7, 0
-  ; 64R6:           dsrlv     $[[T1:[0-9]+]], $5, $[[T0]]
-  ; 64R6:           dsll      $[[T2:[0-9]+]], $4, 1
-  ; 64R6:           not       $[[T3:[0-9]+]], $[[T0]]
-  ; 64R6:           dsllv     $[[T4:[0-9]+]], $[[T2]], $[[T3]]
-  ; 64R6:           or        $[[T5:[0-9]+]], $[[T4]], $[[T1]]
-  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T0]], 32
+  ; 64R6:           dsrlv     $[[T0:[0-9]+]], $5, $7
+  ; 64R6:           dsll      $[[T1:[0-9]+]], $4, 1
+  ; 64R6:           sll       $[[T2:[0-9]+]], $7, 0
+  ; 64R6:           not       $[[T3:[0-9]+]], $[[T2]]
+  ; 64R6:           dsllv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+  ; 64R6:           or        $[[T5:[0-9]+]], $[[T4]], $[[T0]]
+  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T2]], 32
   ; 64R6:           sll       $[[T7:[0-9]+]], $[[T6]], 0
   ; 64R6:           seleqz    $[[T8:[0-9]+]], $[[T5]], $[[T7]]
-  ; 64R6:           dsrlv     $[[T9:[0-9]+]], $4, $[[T0]]
+  ; 64R6:           dsrlv     $[[T9:[0-9]+]], $4, $7
   ; 64R6:           selnez    $[[T10:[0-9]+]], $[[T9]], $[[T7]]
   ; 64R6:           or        $3, $[[T10]], $[[T8]]
   ; 64R6:           jr        $ra
-  ; 64R6:           seleqz    $2, $[[T0]], $[[T7]]
+  ; 64R6:           seleqz    $2, $[[T9]], $[[T7]]
 
   %r = lshr i128 %a, %b
   ret i128 %r