MIPS DSP: add operands to make sure instruction strings are being matched.

[oota-llvm.git] / test / CodeGen / Mips / dsp-r2.ll

diff --git a/test/CodeGen/Mips/dsp-r2.ll b/test/CodeGen/Mips/dsp-r2.ll
index 4656f70636e7c446b3b876cab3840627d8d822c1..631f9e43c23ac3a6ce82225e05f40e384a34aaaa 100644 (file)
--- a/test/CodeGen/Mips/dsp-r2.ll
+++ b/test/CodeGen/Mips/dsp-r2.ll
@@ -539,7 +539,7 @@ declare i32 @llvm.mips.subqh.r.w(i32, i32) nounwind readnone
 
 define i32 @test__builtin_mips_append1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
 entry:
-; CHECK: append
+; CHECK: append ${{[0-9]+}}
 
   %0 = tail call i32 @llvm.mips.append(i32 %a0, i32 %a1, i32 15)
   ret i32 %0
@@ -549,7 +549,7 @@ declare i32 @llvm.mips.append(i32, i32, i32) nounwind readnone
 
 define i32 @test__builtin_mips_balign1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
 entry:
-; CHECK: balign
+; CHECK: balign ${{[0-9]+}}
 
   %0 = tail call i32 @llvm.mips.balign(i32 %a0, i32 %a1, i32 1)
   ret i32 %0
@@ -559,7 +559,7 @@ declare i32 @llvm.mips.balign(i32, i32, i32) nounwind readnone
 
 define i32 @test__builtin_mips_prepend1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
 entry:
-; CHECK: prepend
+; CHECK: prepend ${{[0-9]+}}
 
   %0 = tail call i32 @llvm.mips.prepend(i32 %a0, i32 %a1, i32 15)
   ret i32 %0