MIR Serialization: Change MIR syntax - use custom syntax for MBBs.

[oota-llvm.git] / test / CodeGen / MIR / X86 / expected-alignment-after-align-in-memory-operand.mir

diff --git a/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
index 19ed8e8544e989fc6fb2b74d8e3baf89e864fa75..7ce377f8c5fb10af59a85dc8378b46e0b75a3c22 100644 (file)
--- a/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
+++ b/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
@@ -16,17 +16,15 @@ name:            memory_alignment
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:75: expected an integer literal after 'align'
-      - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align)'
-      - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'
-      - '%xmm2 = FsFLD0SS'
-      - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'
-      - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'
-      - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:70: expected an integer literal after 'align'
+    %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align)
+    %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
+    %xmm2 = FsFLD0SS
+    %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
+    MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
+    MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
+    RETQ
 ...