llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll: s/REQUIRE/REQUIRES/

[oota-llvm.git] / test / CodeGen / Hexagon / newvaluestore.ll

diff --git a/test/CodeGen/Hexagon/newvaluestore.ll b/test/CodeGen/Hexagon/newvaluestore.ll
index ab69b22df57c3747d2e1ab1a00efa68ca5090be5..13cbba2d08e11ea548baedcca7d5583f06f71495 100644 (file)
--- a/test/CodeGen/Hexagon/newvaluestore.ll
+++ b/test/CodeGen/Hexagon/newvaluestore.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4  < %s | FileCheck %s
+; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s
 ; Check that we generate new value store packet in V4
 
 @i = global i32 0, align 4
@@ -7,15 +7,15 @@
 
 define i32 @main() nounwind {
 entry:
-; CHECK: memw(r{{[0-9]+}} + #{{[0-9]+}}) = r{{[0-9]+}}.new
+; CHECK: memw(r{{[0-9]+}}+#{{[0-9]+}}) = r{{[0-9]+}}.new
   %number1 = alloca i32, align 4
   %number2 = alloca i32, align 4
   %number3 = alloca i32, align 4
-  %0 = load i32 * @i, align 4
+  %0 = load i32 , i32 * @i, align 4
   store i32 %0, i32* %number1, align 4
-  %1 = load i32 * @j, align 4
+  %1 = load i32 , i32 * @j, align 4
   store i32 %1, i32* %number2, align 4
-  %2 = load i32 * @k, align 4
+  %2 = load i32 , i32 * @k, align 4
   store i32 %2, i32* %number3, align 4
   ret i32 %0
 }