[ARM] Enable shrink-wrapping by default.

[oota-llvm.git] / test / CodeGen / ARM / intrinsics-crypto.ll

diff --git a/test/CodeGen/ARM/intrinsics-crypto.ll b/test/CodeGen/ARM/intrinsics-crypto.ll
index 96413d341e4ca7a68cdf0138efa39a1efd7ff216..6e5efd85a347b78b194027bfdfe0e4952288b0f8 100644 (file)
--- a/test/CodeGen/ARM/intrinsics-crypto.ll
+++ b/test/CodeGen/ARM/intrinsics-crypto.ll
@@ -1,8 +1,8 @@
 ; RUN: llc < %s -mtriple=armv8 -mattr=+crypto | FileCheck %s
 
 define arm_aapcs_vfpcc <16 x i8> @test_aesde(<16 x i8>* %a, <16 x i8> *%b) {
-  %tmp = load <16 x i8>* %a
-  %tmp2 = load <16 x i8>* %b
+  %tmp = load <16 x i8>, <16 x i8>* %a
+  %tmp2 = load <16 x i8>, <16 x i8>* %b
   %tmp3 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %tmp, <16 x i8> %tmp2)
   ; CHECK: aesd.8 q{{[0-9]+}}, q{{[0-9]+}}
   %tmp4 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %tmp3, <16 x i8> %tmp2)
@@ -15,9 +15,9 @@ define arm_aapcs_vfpcc <16 x i8> @test_aesde(<16 x i8>* %a, <16 x i8> *%b) {
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_sha(<4 x i32> *%a, <4 x i32> *%b, <4 x i32> *%c) {
-  %tmp = load <4 x i32>* %a
-  %tmp2 = load <4 x i32>* %b
-  %tmp3 = load <4 x i32>* %c
+  %tmp = load <4 x i32>, <4 x i32>* %a
+  %tmp2 = load <4 x i32>, <4 x i32>* %b
+  %tmp3 = load <4 x i32>, <4 x i32>* %c
   %scalar = extractelement <4 x i32> %tmp, i32 0
   %resscalar = call i32 @llvm.arm.neon.sha1h(i32 %scalar)
   %res1 = insertelement <4 x i32> undef, i32 %resscalar, i32 0