Add explicit -mtriple=arm-unknown to llvm/test/CodeGen/ARM/disable-tail-calls.ll...

[oota-llvm.git] / test / CodeGen / ARM / bits.ll

diff --git a/test/CodeGen/ARM/bits.ll b/test/CodeGen/ARM/bits.ll
index c5052e5bacbf558df70edcdba69cf0c53a8f36d1..14aa27e90b645ed7e3724465a1efccecb2f0bed6 100644 (file)
--- a/test/CodeGen/ARM/bits.ll
+++ b/test/CodeGen/ARM/bits.ll
@@ -1,36 +1,41 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep and      | wc -l | grep 1 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep orr      | wc -l | grep 1 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep eor      | wc -l | grep 1 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep mov.*lsl | wc -l | grep 1 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep mov.*asr | wc -l | grep 1
+; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
 
-int %f1(int %a, int %b) {
+define i32 @f1(i32 %a, i32 %b) {
 entry:
-       %tmp2 = and int %b, %a          ; <int> [#uses=1]
-       ret int %tmp2
+; CHECK: f1
+; CHECK: and r0, r1, r0
+       %tmp2 = and i32 %b, %a          ; <i32> [#uses=1]
+       ret i32 %tmp2
 }
 
-int %f2(int %a, int %b) {
+define i32 @f2(i32 %a, i32 %b) {
 entry:
-       %tmp2 = or int %b, %a           ; <int> [#uses=1]
-       ret int %tmp2
+; CHECK: f2
+; CHECK: orr r0, r1, r0
+       %tmp2 = or i32 %b, %a           ; <i32> [#uses=1]
+       ret i32 %tmp2
 }
 
-int %f3(int %a, int %b) {
+define i32 @f3(i32 %a, i32 %b) {
 entry:
-       %tmp2 = xor int %b, %a          ; <int> [#uses=1]
-       ret int %tmp2
+; CHECK: f3
+; CHECK: eor r0, r1, r0
+       %tmp2 = xor i32 %b, %a          ; <i32> [#uses=1]
+       ret i32 %tmp2
 }
 
-int %f4(int %a, ubyte %b) {
+define i32 @f4(i32 %a, i32 %b) {
 entry:
-       %tmp3 = shl int %a, ubyte %b            ; <int> [#uses=1]
-       ret int %tmp3
+; CHECK: f4
+; CHECK: lsl
+       %tmp3 = shl i32 %a, %b          ; <i32> [#uses=1]
+       ret i32 %tmp3
 }
 
-int %f5(int %a, ubyte %b) {
+define i32 @f5(i32 %a, i32 %b) {
 entry:
-       %tmp3 = shr int %a, ubyte %b            ; <int> [#uses=1]
-       ret int %tmp3
+; CHECK: f5
+; CHECK: asr
+       %tmp3 = ashr i32 %a, %b         ; <i32> [#uses=1]
+       ret i32 %tmp3
 }