[AArch64] Fix bug in prolog clobbering live reg when shrink wrapping.

[oota-llvm.git] / test / CodeGen / ARM / arm-modifier.ll

diff --git a/test/CodeGen/ARM/arm-modifier.ll b/test/CodeGen/ARM/arm-modifier.ll
index 5e12d8e0355514f1486cacbe4fda36ba1ff69035..67d468e8abd25dcda2270a2b553a3103dd8ac99f 100644 (file)
--- a/test/CodeGen/ARM/arm-modifier.ll
+++ b/test/CodeGen/ARM/arm-modifier.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 -no-integrated-as %s -o - | FileCheck %s
 
 define i32 @foo(float %scale, float %scale2) nounwind {
 entry:
@@ -6,8 +6,8 @@ entry:
   %scale2.addr = alloca float, align 4
   store float %scale, float* %scale.addr, align 4
   store float %scale2, float* %scale2.addr, align 4
-  %tmp = load float* %scale.addr, align 4
-  %tmp1 = load float* %scale2.addr, align 4
+  %tmp = load float, float* %scale.addr, align 4
+  %tmp1 = load float, float* %scale2.addr, align 4
   call void asm sideeffect "vmul.f32    q0, q0, ${0:y} \0A\09vmul.f32    q1, q1, ${0:y} \0A\09vmul.f32    q1, q0, ${1:y} \0A\09", "w,w,~{q0},~{q1}"(float %tmp, float %tmp1) nounwind
   ret i32 0
 }
@@ -49,8 +49,8 @@ entry:
 ; CHECK: stm {{lr|r[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}}
 ; CHECK: adds {{lr|r[0-9]+}}, [[REG1]]
 ; CHECK: ldm {{lr|r[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}}
-%tmp = load i64* @f3_var, align 4
-%tmp1 = load i64* @f3_var2, align 4
+%tmp = load i64, i64* @f3_var, align 4
+%tmp1 = load i64, i64* @f3_var2, align 4
 %0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(i64** @f3_ptr, i64 %tmp, i64 %tmp1) nounwind
 store i64 %0, i64* @f3_var, align 4
 %1 = call i64 asm sideeffect "ldm ${1:m}, ${0:M}\0A\09", "=r,*m"(i64** @f3_ptr) nounwind
@@ -60,9 +60,14 @@ ret void
 
 define i64 @f4(i64* %val) nounwind {
 entry:
-  ;CHECK: f4
-  ;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r0]
-  ;CHECK: mov r0, [[REG1]]
+  ;CHECK-LABEL: f4:
+  ;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
   %0 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [$1]", "=&r,r,*Qo"(i64* %val, i64* %val) nounwind
   ret i64 %0
 }
+
+; PR16490
+define void @f5(i64 %__pu_val) {
+  call void asm sideeffect "$1", "r,i"(i64 %__pu_val, i32 -14)
+  ret void
+}