[ARM] Enable shrink-wrapping by default.

[oota-llvm.git] / test / CodeGen / ARM / 2012-08-23-legalize-vmull.ll

diff --git a/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll b/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
index e8d4fb22a59fd49dcb7aed3d04fa941998beb695..3a851d68f0a4fe9450f7e18ac698afb551d1ac9c 100644 (file)
--- a/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
+++ b/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
@@ -15,7 +15,7 @@
 define void @sextload_v4i8_c(<4 x i8>* %v) nounwind {
 ;CHECK-LABEL: sextload_v4i8_c:
 entry:
-  %0 = load <4 x i8>* %v, align 8
+  %0 = load <4 x i8>, <4 x i8>* %v, align 8
   %v0  = sext <4 x i8> %0 to <4 x i32>
 ;CHECK: vmull
   %v1 = mul <4 x i32>  %v0, <i32 3, i32 3, i32 3, i32 3>
@@ -28,7 +28,7 @@ entry:
 define void @sextload_v2i8_c(<2 x i8>* %v) nounwind {
 ;CHECK-LABEL: sextload_v2i8_c:
 entry:
-  %0   = load <2 x i8>* %v, align 8
+  %0   = load <2 x i8>, <2 x i8>* %v, align 8
   %v0  = sext <2 x i8>  %0 to <2 x i64>
 ;CHECK: vmull
   %v1  = mul <2 x i64>  %v0, <i64 3, i64 3>
@@ -41,7 +41,7 @@ entry:
 define void @sextload_v2i16_c(<2 x i16>* %v) nounwind {
 ;CHECK-LABEL: sextload_v2i16_c:
 entry:
-  %0   = load <2 x i16>* %v, align 8
+  %0   = load <2 x i16>, <2 x i16>* %v, align 8
   %v0  = sext <2 x i16>  %0 to <2 x i64>
 ;CHECK: vmull
   %v1  = mul <2 x i64>  %v0, <i64 3, i64 3>
@@ -56,10 +56,10 @@ entry:
 define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind {
 ;CHECK-LABEL: sextload_v4i8_v:
 entry:
-  %0 = load <4 x i8>* %v, align 8
+  %0 = load <4 x i8>, <4 x i8>* %v, align 8
   %v0  = sext <4 x i8> %0 to <4 x i32>
 
-  %1  = load <4 x i8>* %p, align 8
+  %1  = load <4 x i8>, <4 x i8>* %p, align 8
   %v2 = sext <4 x i8> %1 to <4 x i32>
 ;CHECK: vmull
   %v1 = mul <4 x i32>  %v0, %v2
@@ -72,10 +72,10 @@ entry:
 define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind {
 ;CHECK-LABEL: sextload_v2i8_v:
 entry:
-  %0 = load <2 x i8>* %v, align 8
+  %0 = load <2 x i8>, <2 x i8>* %v, align 8
   %v0  = sext <2 x i8> %0 to <2 x i64>
 
-  %1  = load <2 x i8>* %p, align 8
+  %1  = load <2 x i8>, <2 x i8>* %p, align 8
   %v2 = sext <2 x i8> %1 to <2 x i64>
 ;CHECK: vmull
   %v1 = mul <2 x i64>  %v0, %v2
@@ -88,10 +88,10 @@ entry:
 define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind {
 ;CHECK-LABEL: sextload_v2i16_v:
 entry:
-  %0 = load <2 x i16>* %v, align 8
+  %0 = load <2 x i16>, <2 x i16>* %v, align 8
   %v0  = sext <2 x i16> %0 to <2 x i64>
 
-  %1  = load <2 x i16>* %p, align 8
+  %1  = load <2 x i16>, <2 x i16>* %p, align 8
   %v2 = sext <2 x i16> %1 to <2 x i64>
 ;CHECK: vmull
   %v1 = mul <2 x i64>  %v0, %v2
@@ -106,10 +106,10 @@ entry:
 define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind {
 ;CHECK-LABEL: sextload_v4i8_vs:
 entry:
-  %0 = load <4 x i8>* %v, align 8
+  %0 = load <4 x i8>, <4 x i8>* %v, align 8
   %v0  = sext <4 x i8> %0 to <4 x i32>
 
-  %1  = load <4 x i16>* %p, align 8
+  %1  = load <4 x i16>, <4 x i16>* %p, align 8
   %v2 = sext <4 x i16> %1 to <4 x i32>
 ;CHECK: vmull
   %v1 = mul <4 x i32>  %v0, %v2
@@ -122,10 +122,10 @@ entry:
 define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind {
 ;CHECK-LABEL: sextload_v2i8_vs:
 entry:
-  %0 = load <2 x i8>* %v, align 8
+  %0 = load <2 x i8>, <2 x i8>* %v, align 8
   %v0  = sext <2 x i8> %0 to <2 x i64>
 
-  %1  = load <2 x i16>* %p, align 8
+  %1  = load <2 x i16>, <2 x i16>* %p, align 8
   %v2 = sext <2 x i16> %1 to <2 x i64>
 ;CHECK: vmull
   %v1 = mul <2 x i64>  %v0, %v2
@@ -138,10 +138,10 @@ entry:
 define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind {
 ;CHECK-LABEL: sextload_v2i16_vs:
 entry:
-  %0 = load <2 x i16>* %v, align 8
+  %0 = load <2 x i16>, <2 x i16>* %v, align 8
   %v0  = sext <2 x i16> %0 to <2 x i64>
 
-  %1  = load <2 x i32>* %p, align 8
+  %1  = load <2 x i32>, <2 x i32>* %p, align 8
   %v2 = sext <2 x i32> %1 to <2 x i64>
 ;CHECK: vmull
   %v1 = mul <2 x i64>  %v0, %v2