[ARM] Enable shrink-wrapping by default.

[oota-llvm.git] / test / CodeGen / ARM / 2009-08-02-RegScavengerAssert-Neon.ll

diff --git a/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll b/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
index a656c495f7967dc993f2ff372fd02ff9ef2d4b5f..e277b4cf91a690567b06f7968a6e3bd51c54c7ee 100644 (file)
--- a/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
+++ b/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
@@ -13,17 +13,17 @@ entry:
        %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
        store <4 x i32> %v, <4 x i32>* %v_addr
        store i32 %f, i32* %f_addr
-       %1 = load <4 x i32>* %v_addr, align 16          ; <<4 x i32>> [#uses=1]
-       %2 = load i32* %f_addr, align 4         ; <i32> [#uses=1]
+       %1 = load <4 x i32>, <4 x i32>* %v_addr, align 16               ; <<4 x i32>> [#uses=1]
+       %2 = load i32, i32* %f_addr, align 4            ; <i32> [#uses=1]
        %3 = insertelement <4 x i32> undef, i32 %2, i32 0               ; <<4 x i32>> [#uses=1]
        %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer             ; <<4 x i32>> [#uses=1]
        %5 = mul <4 x i32> %1, %4               ; <<4 x i32>> [#uses=1]
        store <4 x i32> %5, <4 x i32>* %0, align 16
-       %6 = load <4 x i32>* %0, align 16               ; <<4 x i32>> [#uses=1]
+       %6 = load <4 x i32>, <4 x i32>* %0, align 16            ; <<4 x i32>> [#uses=1]
        store <4 x i32> %6, <4 x i32>* %retval, align 16
        br label %return
 
 return:                ; preds = %entry
-       %retval1 = load <4 x i32>* %retval              ; <<4 x i32>> [#uses=1]
+       %retval1 = load <4 x i32>, <4 x i32>* %retval           ; <<4 x i32>> [#uses=1]
        ret <4 x i32> %retval1
 }