[FastISel][AArch64] Optimize compare-and-branch for i1 to use 'tbz'.

[oota-llvm.git] / test / CodeGen / AArch64 / movw-consts.ll

diff --git a/test/CodeGen/AArch64/movw-consts.ll b/test/CodeGen/AArch64/movw-consts.ll
index afdf681c28e6b7c4070af0ed65aef6c1d45f00ef..93c1812717555af6eb6e58fec1f61e8aceb38ff6 100644 (file)
--- a/test/CodeGen/AArch64/movw-consts.ll
+++ b/test/CodeGen/AArch64/movw-consts.ll
@@ -1,71 +1,71 @@
-; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefix=CHECK
 
 define i64 @test0() {
-; CHECK: test0:
+; CHECK-LABEL: test0:
 ; Not produced by move wide instructions, but good to make sure we can return 0 anyway:
 ; CHECK: mov x0, xzr
   ret i64 0
 }
 
 define i64 @test1() {
-; CHECK: test1:
-; CHECK: movz x0, #1
+; CHECK-LABEL: test1:
+; CHECK: orr w0, wzr, #0x1
   ret i64 1
 }
 
 define i64 @test2() {
-; CHECK: test2:
-; CHECK: movz x0, #65535
+; CHECK-LABEL: test2:
+; CHECK: orr w0, wzr, #0xffff
   ret i64 65535
 }
 
 define i64 @test3() {
-; CHECK: test3:
-; CHECK: movz x0, #1, lsl #16
+; CHECK-LABEL: test3:
+; CHECK: orr w0, wzr, #0x10000
   ret i64 65536
 }
 
 define i64 @test4() {
-; CHECK: test4:
-; CHECK: movz x0, #65535, lsl #16
+; CHECK-LABEL: test4:
+; CHECK: orr w0, wzr, #0xffff0000
   ret i64 4294901760
 }
 
 define i64 @test5() {
-; CHECK: test5:
-; CHECK: movz x0, #1, lsl #32
+; CHECK-LABEL: test5:
+; CHECK: orr x0, xzr, #0x100000000
   ret i64 4294967296
 }
 
 define i64 @test6() {
-; CHECK: test6:
-; CHECK: movz x0, #65535, lsl #32
+; CHECK-LABEL: test6:
+; CHECK: orr x0, xzr, #0xffff00000000
   ret i64 281470681743360
 }
 
 define i64 @test7() {
-; CHECK: test7:
-; CHECK: movz x0, #1, lsl #48
+; CHECK-LABEL: test7:
+; CHECK: orr x0, xzr, #0x1000000000000
   ret i64 281474976710656
 }
 
 ; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one
 ; couldn't. Useful even for i64
 define i64 @test8() {
-; CHECK: test8:
-; CHECK: movn w0, #60875
+; CHECK-LABEL: test8:
+; CHECK: movn w0, #{{60875|0xedcb}}
   ret i64 4294906420
 }
 
 define i64 @test9() {
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: movn x0, #0
   ret i64 -1
 }
 
 define i64 @test10() {
-; CHECK: test10:
-; CHECK: movn x0, #60875, lsl #16
+; CHECK-LABEL: test10:
+; CHECK: movn x0, #{{60875|0xedcb}}, lsl #16
   ret i64 18446744069720047615
 }
 
@@ -74,51 +74,51 @@ define i64 @test10() {
 @var32 = global i32 0
 
 define void @test11() {
-; CHECK: test11:
-; CHECK movz {{w[0-9]+}}, #0
+; CHECK-LABEL: test11:
+; CHECK: str wzr
   store i32 0, i32* @var32
   ret void
 }
 
 define void @test12() {
-; CHECK: test12:
-; CHECK: movz {{w[0-9]+}}, #1
+; CHECK-LABEL: test12:
+; CHECK: orr {{w[0-9]+}}, wzr, #0x1
   store i32 1, i32* @var32
   ret void
 }
 
 define void @test13() {
-; CHECK: test13:
-; CHECK: movz {{w[0-9]+}}, #65535
+; CHECK-LABEL: test13:
+; CHECK: orr {{w[0-9]+}}, wzr, #0xffff
   store i32 65535, i32* @var32
   ret void
 }
 
 define void @test14() {
-; CHECK: test14:
-; CHECK: movz {{w[0-9]+}}, #1, lsl #16
+; CHECK-LABEL: test14:
+; CHECK: orr {{w[0-9]+}}, wzr, #0x10000
   store i32 65536, i32* @var32
   ret void
 }
 
 define void @test15() {
-; CHECK: test15:
-; CHECK: movz {{w[0-9]+}}, #65535, lsl #16
+; CHECK-LABEL: test15:
+; CHECK: orr {{w[0-9]+}}, wzr, #0xffff0000
   store i32 4294901760, i32* @var32
   ret void
 }
 
 define void @test16() {
-; CHECK: test16:
+; CHECK-LABEL: test16:
 ; CHECK: movn {{w[0-9]+}}, #0
   store i32 -1, i32* @var32
   ret void
 }
 
 define i64 @test17() {
-; CHECK: test17:
+; CHECK-LABEL: test17:
 
   ; Mustn't MOVN w0 here.
-; CHECK: movn x0, #2
+; CHECK: orr x0, xzr, #0xfffffffffffffffd
   ret i64 -3
 }