[FastISel][AArch64] Optimize compare-and-branch for i1 to use 'tbz'.

[oota-llvm.git] / test / CodeGen / AArch64 / fastcc-reserved.ll

diff --git a/test/CodeGen/AArch64/fastcc-reserved.ll b/test/CodeGen/AArch64/fastcc-reserved.ll
index 1a114a5dc406569de0eaec30f750e80f257d280a..a392619a768dc05dbb34e6823a0bf51d8dd99c0f 100644 (file)
--- a/test/CodeGen/AArch64/fastcc-reserved.ll
+++ b/test/CodeGen/AArch64/fastcc-reserved.ll
@@ -7,13 +7,13 @@
 declare fastcc void @will_pop([8 x i32], i32 %val)
 
 define fastcc void @foo(i32 %in) {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 
   %addr = alloca i8, i32 %in
 
 ; Normal frame setup stuff:
-; CHECK: sub sp, sp,
-; CHECK stp x29, x30
+; CHECK: stp     x29, x30, [sp, #-16]!
+; CHECK: mov     x29, sp
 
 ; Reserve space for call-frame:
 ; CHECK: sub sp, sp, #16
@@ -26,33 +26,33 @@ define fastcc void @foo(i32 %in) {
 ; CHECK-NOT: sub sp, sp, #16
 ; CHECK-NOT: add sp, sp,
 
-; CHECK: ldp x29, x30
-; CHECK: add sp, sp,
+; CHECK: mov     sp, x29
+; CHECK: ldp     x29, x30, [sp], #16
   ret void
 }
 
 declare void @wont_pop([8 x i32], i32 %val)
 
 define void @foo1(i32 %in) {
-; CHECK: foo1:
+; CHECK-LABEL: foo1:
 
   %addr = alloca i8, i32 %in
 ; Normal frame setup again
-; CHECK sub sp, sp,
-; CHECK stp x29, x30
+; CHECK: stp     x29, x30, [sp, #-16]!
+; CHECK: mov     x29, sp
 
 ; Reserve space for call-frame
-; CHECK sub sp, sp, #16
+; CHECK: sub sp, sp, #16
 
   call void @wont_pop([8 x i32] undef, i32 42)
-; CHECK bl wont_pop
+; CHECK: bl wont_pop
 
 ; This time we *do* need to unreserve the call-frame
-; CHECK add sp, sp, #16
+; CHECK: add sp, sp, #16
 
 ; Check for epilogue (primarily to make sure sp spotted above wasn't
 ; part of it).
-; CHECK: ldp x29, x30
-; CHECK: add sp, sp,
+; CHECK: mov     sp, x29
+; CHECK: ldp     x29, x30, [sp], #16
   ret void
 }