Change memcpy/memset/memmove to have dest and source alignments.

[oota-llvm.git] / test / CodeGen / AArch64 / arm64-stur.ll

diff --git a/test/CodeGen/AArch64/arm64-stur.ll b/test/CodeGen/AArch64/arm64-stur.ll
index 5f4cb9f3d95a9c18ddf8ef2836bff3f3506560a2..f8675cb6cda8130398b1fdfe18122290961c4eca 100644 (file)
--- a/test/CodeGen/AArch64/arm64-stur.ll
+++ b/test/CodeGen/AArch64/arm64-stur.ll
@@ -55,11 +55,11 @@ define void @foo(%struct.X* nocapture %p) nounwind optsize ssp {
 ; CHECK-NEXT: ret
   %B = getelementptr inbounds %struct.X, %struct.X* %p, i64 0, i32 1
   %val = bitcast i64* %B to i8*
 ; CHECK-NEXT: ret
   %B = getelementptr inbounds %struct.X, %struct.X* %p, i64 0, i32 1
   %val = bitcast i64* %B to i8*

-  call void @llvm.memset.p0i8.i64(i8* %val, i8 0, i64 16, i32 1, i1 false)
+  call void @llvm.memset.p0i8.i64(i8* %val, i8 0, i64 16, i1 false)

   ret void
 }
 
   ret void
 }
 

-declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind

 
 ; Unaligned 16b stores are split into 8b stores for performance.
 ; radar://15424193
 
 ; Unaligned 16b stores are split into 8b stores for performance.
 ; radar://15424193