[AArch64] Fix bug in prolog clobbering live reg when shrink wrapping.

[oota-llvm.git] / test / CodeGen / AArch64 / arm64-misaligned-memcpy-inline.ll

diff --git a/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll b/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
index 7ecf214b4bede56070825995532767cdbe10de2d..85572f2cf0f8cc8dfa6b46e85e43d52b8eb3a819 100644 (file)
--- a/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
+++ b/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
@@ -7,8 +7,8 @@ define void @t0(i8* %out, i8* %in) {
 ; CHECK:         orr w2, wzr, #0x10
 ; CHECK-NEXT:    bl _memcpy
 entry:
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %out, i8* %in, i64 16, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %out, i8* %in, i64 16, i32 1, i1 false)
   ret void
 }
 
-declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1)
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1)