; Speculatively execute division by zero.
; The sdiv/udiv instructions do not trap when the divisor is zero, so they are
; safe to speculate.
-; CHECK: speculate_division
-; CHECK-NOT: cmp
-; CHECK: sdiv
-; CHECK: cmp
-; CHECK-NEXT: ccmp
+; CHECK-LABEL: speculate_division:
+; CHECK: cmp w0, #1
+; CHECK: sdiv [[DIVRES:w[0-9]+]], w1, w0
+; CHECK: ccmp [[DIVRES]], #16, #0, ge
+; CHECK: b.gt [[BLOCK:LBB[0-9_]+]]
+; CHECK: bl _foo
+; CHECK: [[BLOCK]]:
+; CHECK: orr w0, wzr, #0x7
define i32 @speculate_division(i32 %a, i32 %b) nounwind ssp {
entry:
%cmp = icmp sgt i32 %a, 0
}
; CHECK-LABEL: select_and
-define i64 @select_and(i32 %v1, i32 %v2, i64 %a, i64 %b) {
-; CHECK: cmp
-; CHECK: ccmp{{.*}}, #0, ne
-; CHECK: csel{{.*}}, lt
- %1 = icmp slt i32 %v1, %v2
- %2 = icmp ne i32 5, %v2
+define i64 @select_and(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {
+; CHECK: cmp w1, #5
+; CHECK-NEXT: ccmp w0, w1, #0, ne
+; CHECK-NEXT: csel x0, x2, x3, lt
+; CHECK-NEXT: ret
+ %1 = icmp slt i32 %w0, %w1
+ %2 = icmp ne i32 5, %w1
%3 = and i1 %1, %2
- %sel = select i1 %3, i64 %a, i64 %b
+ %sel = select i1 %3, i64 %x2, i64 %x3
ret i64 %sel
}
; CHECK-LABEL: select_or
-define i64 @select_or(i32 %v1, i32 %v2, i64 %a, i64 %b) {
-; CHECK: cmp
-; CHECK: ccmp{{.*}}, #8, eq
-; CHECK: csel{{.*}}, lt
- %1 = icmp slt i32 %v1, %v2
- %2 = icmp ne i32 5, %v2
+define i64 @select_or(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {
+; CHECK: cmp w1, #5
+; CHECK-NEXT: ccmp w0, w1, #8, eq
+; CHECK-NEXT: csel x0, x2, x3, lt
+; CHECK-NEXT: ret
+ %1 = icmp slt i32 %w0, %w1
+ %2 = icmp ne i32 5, %w1
%3 = or i1 %1, %2
- %sel = select i1 %3, i64 %a, i64 %b
+ %sel = select i1 %3, i64 %x2, i64 %x3
ret i64 %sel
}
; CHECK-LABEL: select_complicated
define i16 @select_complicated(double %v1, double %v2, i16 %a, i16 %b) {
-; CHECK: fcmp
-; CHECK: fccmp{{.*}}, #4, ne
-; CHECK: fccmp{{.*}}, #1, ne
-; CHECK: fccmp{{.*}}, #4, vc
-; CEHCK: csel{{.*}}, eq
+; CHECK: ldr [[REG:d[0-9]+]],
+; CHECK: fcmp d0, d2
+; CHECK-NEXT: fmov d2, #13.00000000
+; CHECK-NEXT: fccmp d1, d2, #4, ne
+; CHECK-NEXT: fccmp d0, d1, #1, ne
+; CHECK-NEXT: fccmp d0, d1, #4, vc
+; CEHCK-NEXT: csel w0, w0, w1, eq
%1 = fcmp one double %v1, %v2
%2 = fcmp oeq double %v2, 13.0
%3 = fcmp oeq double %v1, 42.0
%sel = select i1 %or1, i16 %a, i16 %b
ret i16 %sel
}
+
+; CHECK-LABEL: gccbug
+define i64 @gccbug(i64 %x0, i64 %x1) {
+; CHECK: cmp x1, #0
+; CHECK-NEXT: ccmp x0, #2, #0, eq
+; CHECK-NEXT: ccmp x0, #4, #4, ne
+; CHECK-NEXT: orr w[[REGNUM:[0-9]+]], wzr, #0x1
+; CHECK-NEXT: cinc x0, x[[REGNUM]], eq
+; CHECK-NEXT: ret
+ %cmp0 = icmp eq i64 %x1, 0
+ %cmp1 = icmp eq i64 %x0, 2
+ %cmp2 = icmp eq i64 %x0, 4
+
+ %or = or i1 %cmp2, %cmp1
+ %and = and i1 %or, %cmp0
+
+ %sel = select i1 %and, i64 2, i64 1
+ ret i64 %sel
+}
+
+; CHECK-LABEL: select_ororand
+define i32 @select_ororand(i32 %w0, i32 %w1, i32 %w2, i32 %w3) {
+; CHECK: cmp w3, #4
+; CHECK-NEXT: ccmp w2, #2, #0, gt
+; CHECK-NEXT: ccmp w1, #13, #2, ge
+; CHECK-NEXT: ccmp w0, #0, #4, ls
+; CHECK-NEXT: csel w0, w3, wzr, eq
+; CHECK-NEXT: ret
+ %c0 = icmp eq i32 %w0, 0
+ %c1 = icmp ugt i32 %w1, 13
+ %c2 = icmp slt i32 %w2, 2
+ %c4 = icmp sgt i32 %w3, 4
+ %or = or i1 %c0, %c1
+ %and = and i1 %c2, %c4
+ %or1 = or i1 %or, %and
+ %sel = select i1 %or1, i32 %w3, i32 0
+ ret i32 %sel
+}
+
+; CHECK-LABEL: select_noccmp1
+define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
+; CHECK-NOT: CCMP
+ %c0 = icmp slt i64 %v1, 0
+ %c1 = icmp sgt i64 %v1, 13
+ %c2 = icmp slt i64 %v3, 2
+ %c4 = icmp sgt i64 %v3, 4
+ %and0 = and i1 %c0, %c1
+ %and1 = and i1 %c2, %c4
+ %or = or i1 %and0, %and1
+ %sel = select i1 %or, i64 0, i64 %r
+ ret i64 %sel
+}
+
+@g = global i32 0
+
+; Should not use ccmp if we have to compute the or expression in an integer
+; register anyway because of other users.
+; CHECK-LABEL: select_noccmp2
+define i64 @select_noccmp2(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
+; CHECK-NOT: CCMP
+ %c0 = icmp slt i64 %v1, 0
+ %c1 = icmp sgt i64 %v1, 13
+ %or = or i1 %c0, %c1
+ %sel = select i1 %or, i64 0, i64 %r
+ %ext = sext i1 %or to i32
+ store volatile i32 %ext, i32* @g
+ ret i64 %sel
+}